Similar Items: A mass memory system for satellites using field programmable gate arrays and synchronous DRAM
- Development of superconducting field-programmable gate array and supporting EDA software
- A reconfigurable array processor
- The design and testing of a superconducting programmable gate array
- Identifying worst case test vectors for FPGA exposed to total ionization dose using design for testability techniques
- The implementation of a microprocessor in a FPGA
- An FPGA-based adaptive forward error correction protocol for cubeSats
Author: Blanckenberg, M. M.
- Auditory middle-latency evoked potential measurement and averaging methods
- Design of a haptic controller for excavators
- The design of a hysteroscopy simulator
- Efficient registration of limited field of view ocular fundus imagery
- The selection and single event upset testing of a DSP processor for a LEO satellite
- Video camera design and implementation for telemedicine application