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Similar Items: Emerging 2D Materials for Beyond von Neumann Computing: A Perspective

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EMiX: Emulating Beyond Single-FPGA Limits
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Beyond Static Policies: Exploring Dynamic Policy Selection for Single-Thread Performance Optimization
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RecFlash: Fast Recommendation System on In-Storage Computing with Frequency-Based Data Mapping
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RCW-CIM: A Digital CIM-based LLM Accelerator with Read-Compute/Write
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NVLLM: A 3D NAND-Centric Architecture Enabling Edge on-Device LLM Inference
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MCFlash: Bulk Bitwise Processing in 3D NAND with Dynamic Sensing and Multi-level Encoding
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Sparse-on-Dense: Area and Energy-Efficient Computing of Sparse Neural Networks on Dense Matrix Multiplication Accelerators
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Reconfigurable Computing Challenge: Real-Time Graph Neural Networks for Online Event Selection in Big Science
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A virtually connected probabilistic computer as a solver for higher-order, densely connected, or reconfigurable combinatorial optimisation problems
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A PVT-Resilient Subthreshold SRAM-Based In-Memory Computing Accelerator with In-Situ Regulation for Energy-Efficient Spiking Neural Networks
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Design Conductor 2.0: An agent builds a TurboQuant inference accelerator in 80 hours
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EDA-Schema-V2: A Multimodal Schema, Open Datasets, and Benchmarks for Machine Learning in Digital Physical Design
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AHASD: Asynchronous Heterogeneous Architecture for LLM Adaptive Drafting Speculative Decoding on Mobile Devices
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No Tile Left Behind: Multiprogramming for Surface-Code Architectures
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At the Edge of the Heart: ULP FPGA-Based CNN for On-Device Cardiac Feature Extraction in Smart Health Sensors for Astronauts
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RAG-Enhanced Kernel-Based Heuristic Synthesis (RKHS): A Structured Methodology Using Large Language Models for Hardware Design
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AMMA: A Multi-Chiplet Memory-Centric Architecture for Low-Latency 1M Context Attention Serving
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Efficient, VRAM-Constrained xLM Inference on Clients
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Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
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SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation
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VitaLLM: A Versatile, Ultra-Compact Ternary LLM Accelerator with Dependency-Aware Scheduling
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CuLifter: Lifting GPU Binaries to Typed IR
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HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs
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AME-PIM: Can Memory be Your Next Tensor Accelerator?