Channels - Sieve: Dynamic Expert-Aware PIM Acceleration for Evolving Mixture-of-Experts Models :: FRELIP Discovery

Similar Items: Sieve: Dynamic Expert-Aware PIM Acceleration for Evolving Mixture-of-Experts Models

Quick Look
AME-PIM: Can Memory be Your Next Tensor Accelerator?
Quick Look
AxMoE: Characterizing the Impact of Approximate Multipliers on Mixture-of-Experts DNN Architectures
Quick Look
TokenStack: A Heterogeneous HBM-PIM Architecture and Runtime for Efficient LLM Inference
Quick Look
HyDRA: Deadline and Reuse-Aware Cacheability for Hardware Accelerators
Quick Look
HyDRA: Deadline and Reuse-Aware Cacheability for Hardware Accelerators
Quick Look
VitaLLM: A Versatile, Ultra-Compact Ternary LLM Accelerator with Dependency-Aware Scheduling
Quick Look
UniPool: A Globally Shared Expert Pool for Mixture-of-Experts
Quick Look
Routers Learn the Geometry of Their Experts: Geometric Coupling in Sparse Mixture-of-Experts
Quick Look
TLX: Hardware-Native, Evolvable MIMW GPU Compiler for Large-scale Production Environments
Quick Look
RFAmpDesigner: A Self-Evolving Multi-Agent LLM Framework for Automated Radio Frequency Amplifier Design
Quick Look
LLM-Driven Design Space Exploration of FPGA-based Accelerators
Quick Look
AccelSync: Verifying Synchronization Coverage in Accelerator Pipeline Programs
Quick Look
EMO: Pretraining Mixture of Experts for Emergent Modularity
Quick Look
RCW-CIM: A Digital CIM-based LLM Accelerator with Read-Compute/Write
Quick Look
DPU or GPU for Accelerating Neural Networks Inference -- Why not both? Split CNN Inference
Quick Look
PoTAcc: A Pipeline for End-to-End Acceleration of Power-of-Two Quantized DNNs
Quick Look
VitaLLM: A Versatile and Tiny Accelerator for Mixed-Precision LLM Inference on Edge Devices
Quick Look
Sparse-on-Dense: Area and Energy-Efficient Computing of Sparse Neural Networks on Dense Matrix Multiplication Accelerators
Quick Look
Design Conductor 2.0: An agent builds a TurboQuant inference accelerator in 80 hours
Quick Look
Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
Quick Look
EULER-ADAS: Energy-Efficient & SIMD-Unified Logarithmic-Posit Engine for Precision-Reconfigurable Approximate ADAS Acceleration
Quick Look
A PVT-Resilient Subthreshold SRAM-Based In-Memory Computing Accelerator with In-Situ Regulation for Energy-Efficient Spiking Neural Networks
Quick Look
31.1 A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding
Quick Look
PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation