Haridy, O. F. (2013). Synthesizable delay line architectures for digitally controlled voltage regulators. AUC Knowledge Fountain.
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Chicago Style (17th ed.) Citation
Haridy, Omar Fathy. Synthesizable Delay Line Architectures for Digitally Controlled Voltage Regulators. AUC Knowledge Fountain, 2013.
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MLA (9th ed.) Citation
Haridy, Omar Fathy. Synthesizable Delay Line Architectures for Digitally Controlled Voltage Regulators. AUC Knowledge Fountain, 2013.
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Warning: These citations may not always be 100% accurate.