Macro-model of through silicon vias (tsvs) arrays - Ahmed, Karim (AUC Knowledge Fountain, 2013)
As continued scaling down of transistors becomes increasingly difficult due to physical and technical issues like the increase of leakage power and total power consumption, overall, 3D integration is now considered a viable solution to get a higher bandwidth and power efficiency. Use of Through-silicon-vias (TSVs), which connects stacked structures die-to-die, is expected to be one of the most important techniques enabling 3D integration. As the number of through silicon Vias (TSVs) exists in the same chip is increasing, an algorithm to build a macro-model is needed to find inter-relationship between TSVs. There are different coupling parameters that exist between TSVs like: capacitive, inductive and resistive coupling. This work provides an algorithm to build a macro-model of an array of TSVs where only capacitive coupling is considered, as it is expected to be the dominating parameter.Using a simulation based technique, where characterization for bundles of TSVs were done and a scaling equation that can give the variationsoccur to capacitance value with scaling the physical dimensions of the TSV (pitch, radius, length and dielectric thickness (tox)) is proposed. The considered ranges for the physical parameters are: radius (from 1um to 10um), tox (from 0.1um to 0.5 um), length (from 10um to 100um) and pitch (from 10um to 95um). Using theproposed algorithm, a macro model can be built in a negligible time, which provides lots of time saving compared to hours required by other tools such as EM simulators or device simulators. The average error range 3% to 6%and a maximum cumulative error of algorithm and usage of scaling equation is 18.2% that occurs at very few dimensions and in very few capacitances from the extracted capacitance values, for both self and coupling capacitance.