Design and Implementation of UVM-based Verification Framework for Deep Learning Accelerators - Aboudeif, Randa Ahmed Hussein (AUC Knowledge Fountain, 2025)
Recent advancements in deep learning (DL) have made hardware accelerators, known as deep learning accelerators (DLAs), a preferred solution for numerous high-performance computing (HPC) applications, including speech recognition, computer vision, and image classification. DLAs are composed of hundreds of parallel processing engines to speed up computations and can gain access to pre-trained networks from the cloud or through on-chip memory to implement the DNN inference process. DLA verification is becoming an important and challenging phase. The verification process is required to handle the complex DLA design. Moreover, the reliability of DLAs is critical for assessment as they are involved in safety-critical applications, especially with the noticeable increase in sensor faults, adversarial attacks, and hardware functional errors occurring in DLAs, resulting in violations of safety and reliability requirements. In our thesis, a novel, scalable, reusable, and efficient verification framework for deep learning hardware accelerators using the UVM is introduced. The proposed framework is to create a scalable and reusable UVM verification testbench for testing deep learning accelerators with simulation, emulation, and FPGA prototyping by running different testing scenarios for DNNs with multiple configurations. Moreover, the proposed framework has a scalable error injection methodology for testing the trustworthiness of deep learning accelerators. The proposed error injection methodology is reliable and has complete access to the DNN data path between layers and the DLA configurations. The proposed framework is applicable to different DNN architectures.