A Novel Design-for-Test flow using LibreLane - Gaber, Mohamed E (AUC Knowledge Fountain, 2026)
Design-for-testing is a crucial element of application-specific integrated circuit design, yet, in the nascent open-source electronic design automation scene, the solutions for it are sorely limited. Design-for-test-enabled chips allow defects to be caught early on in the manufacturing process, avoiding incurring huge costs if hardware with defective chips is shipped to equipment manufacturers or, worse, end-users. Yet, the current open-source solutions rely on a brute-force utility that does not scale and negatively impacts the design by holding design-for-testing features as co-equal with the design’s regular operation, and a nominally layout-aware solution that does not holistically integrate into a larger flow. This work architects and implements a novel design-for-test flow designed as a plugin for the popular LibreLane flow infrastructure, the successor to the single most used application-specific integrated circuit design flow in existence. Coalescing a number of existing and ad-hoc developed open-source tools, it shows that open-source electronic design automation tools can indeed be used to create macros and chips that are design-for-testing-enabled, with rapid test pattern generation, area savings by using scannable flip-flops, as well as layout-aware placement that appreciably decreases routing time in comparison to existing approaches. It investigates various strategies for ordering of a scan chain, comparing the current approaches of ordering a netlist, or a greedy closest-first algorithm, to the decades of work on optimizing the traveling salesman problem. It compares the results across three strategies and two process design kits.