Herbst, H., & Fourie, C. (2021). Gate-level superconductor integrated circuit fabrication process modelling for improved layout extraction. Stellenbosch : Stellenbosch University, 2021.
Successfully copied to clipboard
Copying to clipboard failed
Chicago Style (17th ed.) Citation
Herbst, Heinrich, and Coenrad Fourie. Gate-level Superconductor Integrated Circuit Fabrication Process Modelling for Improved Layout Extraction. Stellenbosch : Stellenbosch University, 2021, 2021.
Successfully copied to clipboard
Copying to clipboard failed
MLA (9th ed.) Citation
Herbst, Heinrich, and Coenrad Fourie. Gate-level Superconductor Integrated Circuit Fabrication Process Modelling for Improved Layout Extraction. Stellenbosch : Stellenbosch University, 2021, 2021.
Successfully copied to clipboard
Copying to clipboard failed
Warning: These citations may not always be 100% accurate.