(2026). Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory. IEEE Journal of the Electron Devices Society.
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Chicago Style (17th ed.) Citation
"Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory."
IEEE Journal of the Electron Devices Society 2026.
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MLA (9th ed.) Citation
"Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory."
IEEE Journal of the Electron Devices Society, 2026.
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Warning: These citations may not always be 100% accurate.