APA (7th ed.) Citation
(2017). State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers. VLSI Design.
Chicago Style (17th ed.) Citation
"State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers." VLSI Design 2017.
MLA (9th ed.) Citation
"State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers." VLSI Design, 2017.
Warning: These citations may not always be 100% accurate.