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State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

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Published in:VLSI Design
Format: Online Article RSS Article
Published: 2017
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container_title VLSI Design
description
discipline_display Computer Science
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institution FRELIP
journal_source_facet VLSI Design
publishDate 2017
publishDateSort 2017
record_format rss_article
spellingShingle State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
Computer Science
General
Computer Science
sub_discipline_display General
sub_discipline_facet General
subject_display Computer Science
General
Computer Science
Computer Science
General
Computer Science
subject_facet Computer Science
General
Computer Science
title State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
title_auth State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
title_full State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
title_fullStr State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
title_full_unstemmed State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
title_short State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
title_sort state-transition-aware spilling heuristic for mlc stt-ram-based registers
topic Computer Science
General
Computer Science
url https://www.hindawi.com/journals/vlsi/2017/1030249/