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Silicon Showdown: Performance, Efficiency, and Ecosystem Barriers in Consumer-Grade LLM Inference
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VitaLLM: A Versatile and Tiny Accelerator for Mixed-Precision LLM Inference on Edge Devices
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A PVT-Resilient Subthreshold SRAM-Based In-Memory Computing Accelerator with In-Situ Regulation for Energy-Efficient Spiking Neural Networks
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DPU or GPU for Accelerating Neural Networks Inference -- Why not both? Split CNN Inference
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Low-rank Preconditioning in Beamspace Domain For Massive MU-MIMO Long-Term Beamforming
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Performance and Energy Benefits of MRDIMMs
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Cerberus: Cross-Layer ECC Co-Design for Robust and Efficient Memory Protection
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A Protocol-Independent Transport Architecture
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ViM-Q: Scalable Algorithm-Hardware Co-Design for Vision Mamba Model Inference on FPGA
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RV-IM100: Quantifying ISA Extension, Datapath Width, and Pipeline Depth Trade-offs in RISC-V Microarchitectures
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PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation
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SPEC CPU: The Next Generation
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Understanding Simulated Architecture via gem5 Call-Stack Profiling
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AMSnet-q: Unsupervised Circuit Identification and Performance Labeling for AMS Circuits
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Evolution of NVENC Efficiency: A Longitudinal Analysis of HQ and UHQ Tuning Efficiency, Latency and Energy Trade-offs
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SPEC CPU2026: Characterization, Representativeness, and Cross-Suite Comparison
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Design and Implementation of BNN-Based Object Detection on FPGA
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On-Orbit Real-Time Wildfire Detection Under On-Board Constraints
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PoTAcc: A Pipeline for End-to-End Acceleration of Power-of-Two Quantized DNNs
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XtraMAC: An Efficient MAC Architecture for Mixed-Precision LLM Inference on FPGA
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