Results for VLSI Design Showing 1 - 12 results of 12 Laminas_Feed_Writer 2 (https://getlaminas.org) https://search.frelip.org/Search/Results?sort=last_indexed+desc&limit=50&lookfor=VLSI+Design&type=AllFields&lng=en 12 0 50 The design of a reliable minimum area VLSI circuit Wed, 10 Jun 2026 12:44:52 +0000 https://search.frelip.org/Record/oai:scholar.sun.ac.za:10019.1%2F67107 https://search.frelip.org/Record/oai:scholar.sun.ac.za:10019.1%2F67107 Nel, Louis Fourie Thesis 2012 Nel, Louis Fourie 0 Rapid single flux quantum very large scale integration Wed, 10 Jun 2026 12:43:47 +0000 https://search.frelip.org/Record/oai:scholar.sun.ac.za:10019.1%2F49734 https://search.frelip.org/Record/oai:scholar.sun.ac.za:10019.1%2F49734 Gross, Peter Alan Thesis 2012 Gross, Peter Alan 0 Physical Effects on the Worst-Case Delay Analysis and Signal Integrity of Buses and Spirals Wed, 10 Jun 2026 12:35:55 +0000 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-3380 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-3380 Mahany, Mahmoud Thesis 2024 Mahany, Mahmoud 0 Fast and Accurate Automatic Design of Spiral Inductors from High-Level Specification Wed, 10 Jun 2026 12:35:54 +0000 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-3297 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-3297 Ismail, Heba Thesis 2024 Ismail, Heba 0 Single Event Transient Sensitivity Measurement and Worst-Case Test Vector Exploration for ASIC Devices Exposed to Space Single Event Environment Wed, 10 Jun 2026 12:35:53 +0000 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-2913 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-2913 Wael, Mohamed Thesis 2022 Wael, Mohamed 0 Machine Learning Applications to Static Timing Analysis Wed, 10 Jun 2026 12:35:53 +0000 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-2950 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-2950 Raslan, Waseem Mohamed Thesis 2022 Raslan, Waseem Mohamed 0 Integrated Circuits Parasitic Capacitance Extraction Using Machine Learning and its Application to Layout Optimization Wed, 10 Jun 2026 12:35:53 +0000 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-2955 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-2955 Saleh, Mohamed Saleh Abouelyazid Thesis 2022 Saleh, Mohamed Saleh Abouelyazid 0 Modeling the phase step response of digital Bang-Bang PLLs Wed, 10 Jun 2026 12:35:50 +0000 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-2590 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-2590 Abdelfattah, Moataz Thesis 2013 Abdelfattah, Moataz 0 Layout regularity metric as a fast indicator of process variations Wed, 10 Jun 2026 12:35:47 +0000 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-2242 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-2242 Swillam, Esraa AbdelAzim AbdelHamid Thesis 2014 Swillam, Esraa AbdelAzim AbdelHamid 0 On-chip signaling techniques for high-speed Serdes transceivers Wed, 10 Jun 2026 12:35:47 +0000 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-2244 https://search.frelip.org/Record/oai:fount.aucegypt.edu:etds-2244 Tadros, Ramy Nagy Thesis 2015 Tadros, Ramy Nagy 0 Spline wavelet image coding and synthesis for a VLSI based difference engine Wed, 10 Jun 2026 12:32:29 +0000 https://search.frelip.org/Record/oai:open.uct.ac.za:11427%2F13527 https://search.frelip.org/Record/oai:open.uct.ac.za:11427%2F13527 Marais, Patrick Thesis 2015 Marais, Patrick 0 A hardware implementation of a Viterbi decoder for a (3,2/3) TCM code Wed, 10 Jun 2026 12:31:47 +0000 https://search.frelip.org/Record/oai:open.uct.ac.za:11427%2F20182 https://search.frelip.org/Record/oai:open.uct.ac.za:11427%2F20182 Horwitz, Michael Richard Thesis 2016 Horwitz, Michael Richard 0