A hardware implementation of a Viterbi decoder for a (3,2/3) TCM code by Horwitz, Michael Richard

“…It was the specific intention of the thesis to design a system that could be implemented on standard Field Programmable Gate Arrays (FPGA) yet still be able to cope with high bit rates. …”
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A second generation SUNSAT RAMDISK by Rust, A. N.

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From high-speed superconducting devices to nanosensors by Perold, Willem

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Development of a multilevel converter topology for transformer-less connection of renewable energy systems by Ajayi-Obe, Akinola Ayodeji

“…The proposed converter topology, known as the "tapped inductor quasi-Z-source nested neutral-point-clamped (NNPC) converter," has been analyzed, and designed, and a prototype of the topology developed for experimental verification. A field-programmable gate array (FPGA)-based modulation technique and voltage balancing control technique for maintaining the clamping capacitor voltages was developed. …”
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Unsupervised anomaly detection for the ATLAS Level-1 Trigger by Stern, Thomas

“…The detector collects far more data than can be processed, resulting in over 99% of all data being deleted in real time by the Level-1 Trigger—a chain of field-programmable gate arrays optimized to accept data relevant to the physics processes under study and reject unwanted data. …”
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High frame rate marker detection for single camera-based localisation by Pretorius, Schalk

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The design of a high speed topology for a QPSK demodulator with emphasis on the synchronization algorithms needed for demodulation by Booysen, Samuel

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Practical implementation of long-horizon direct model predictive control by Dorfling, Martinus David

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Generalized model predictive pulse pattern control based on small-signal modelling by Dorfling, Martinus

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A domain specific language for facilitating automatic parallelization and placement of SDR patterns into heterogeneous computing architectures by Mohapi, Lerato Jerfree

“…The OptiSDR target HCAs are composed of graphics processing units (GPUs), multi-core central processing units (MCPUs), and field programmable gate arrays (FPGAs). The methodology used to implement the OptiSDR DSL involved an extensive review process of existing SDR tools and the extent to which they address the complexities associated with parallel programming and optimizing SDR applications for execution in HCAs. …”
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SdrLift: A Domain-Specific Intermediate Hardware Synthesis Framework for Prototyping Software-Defined Radios by Tsoeunyane, Lekhobola Joachim

“…Modern design of Software-Defined Radio (SDR) applications is based on Field Programmable Gate Arrays (FPGA) due to their ability to be configured into solution architectures that are well suited to domain-specific problems while achieving the best trade-off between performance, power, area, and flexibility. …”
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Long-Horizon direct model predictive control of an active capacitor for ripple energy compensation in single-phase DC-to-AC converters by Chingwena, Macyln

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A digital low-level radio frequency control system for the particle accelerators at iThemba LABS by Duckitt, William

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Accelerator-based look-up table for coarse-grained molecular dynamics computations by Gangopadhyay, Ananya

“…Both fully-atomistic and coarse-grained developers have accelerated packages using high-performance parallel computing platforms such as multi-core CPU clusters, Field Programmable Gate Arrays (FPGAs) and Graphics Processing Units (GPUs). …”
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