Development of a multilevel converter topology for transformer-less connection of renewable energy systems by Ajayi-Obe, Akinola Ayodeji

“…The proposed converter topology, known as the "tapped inductor quasi-Z-source nested neutral-point-clamped (NNPC) converter," has been analyzed, and designed, and a prototype of the topology developed for experimental verification. A field-programmable gate array (FPGA)-based modulation technique and voltage balancing control technique for maintaining the clamping capacitor voltages was developed. …”
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A comparative analysis of academic literacy specifications for a standardised test and academic literacy requirements for reading and writing in a range of disciplinary contexts by Scholtz, Desiree Leonora

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From high-speed superconducting devices to nanosensors by Perold, Willem

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High frame rate marker detection for single camera-based localisation by Pretorius, Schalk

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The design of a high speed topology for a QPSK demodulator with emphasis on the synchronization algorithms needed for demodulation by Booysen, Samuel

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Generalized model predictive pulse pattern control based on small-signal modelling by Dorfling, Martinus

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Architectural Level Computational Hardware Abstraction: A New Programming Language for FPGA Projects by Taylor, John-Philip

“…Recent years have seen vast improvements to the capability of programmable processing platforms, especially field programmable gate arrays, or FPGAs. …”
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SdrLift: A Domain-Specific Intermediate Hardware Synthesis Framework for Prototyping Software-Defined Radios by Tsoeunyane, Lekhobola Joachim

“…Modern design of Software-Defined Radio (SDR) applications is based on Field Programmable Gate Arrays (FPGA) due to their ability to be configured into solution architectures that are well suited to domain-specific problems while achieving the best trade-off between performance, power, area, and flexibility. …”
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Unsupervised anomaly detection for the ATLAS Level-1 Trigger by Stern, Thomas

“…The detector collects far more data than can be processed, resulting in over 99% of all data being deleted in real time by the Level-1 Trigger—a chain of field-programmable gate arrays optimized to accept data relevant to the physics processes under study and reject unwanted data. …”
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Accelerator-based look-up table for coarse-grained molecular dynamics computations by Gangopadhyay, Ananya

“…Both fully-atomistic and coarse-grained developers have accelerated packages using high-performance parallel computing platforms such as multi-core CPU clusters, Field Programmable Gate Arrays (FPGAs) and Graphics Processing Units (GPUs). …”
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A digital low-level radio frequency control system for the particle accelerators at iThemba LABS by Duckitt, William

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