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Search Results - field programme rate array
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An FPGA-based adaptive forward error correction protocol for cubeSats
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Total ionizing dose mitigation by means of reconfigurable FPGA computing
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The design and implementation of a video compression development board
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FPGA implementation of a network coding capable switch
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High frame rate marker detection for single camera-based localisation
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An electronically focused multiple beam side scan sonar
Published 2017“…This thesis describes a microprocessor controlled dynamically focused side scan sonar where high resolution and high image acquisition rates are achieved. Dynamic focusing prevents the depth of field limitations of fixed focus arrays by updating the array phases at regular intervals so as to create a focal point which recedes from the array in synchronism with the returning echoes from the transmitted pulse. …”
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Evaluating FFT Implementations Developed for use on FPGA Hardware
Published 2024“…Field Programmable Gate Arrays (FPGAs) are a type of hardware commonly used to perform the various computations required to process incoming radio signals, including the FFT. …”
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Development of a multilevel converter topology for transformer-less connection of renewable energy systems
Published 2023“…The proposed converter topology, known as the "tapped inductor quasi-Z-source nested neutral-point-clamped (NNPC) converter," has been analyzed, and designed, and a prototype of the topology developed for experimental verification. A field-programmable gate array (FPGA)-based modulation technique and voltage balancing control technique for maintaining the clamping capacitor voltages was developed. …”
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The design of a high speed topology for a QPSK demodulator with emphasis on the synchronization algorithms needed for demodulation
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SdrLift: A Domain-Specific Intermediate Hardware Synthesis Framework for Prototyping Software-Defined Radios
Published 2021“…Modern design of Software-Defined Radio (SDR) applications is based on Field Programmable Gate Arrays (FPGA) due to their ability to be configured into solution architectures that are well suited to domain-specific problems while achieving the best trade-off between performance, power, area, and flexibility. …”
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A hardware implementation of a Viterbi decoder for a (3,2/3) TCM code
Published 2016“…It was the specific intention of the thesis to design a system that could be implemented on standard Field Programmable Gate Arrays (FPGA) yet still be able to cope with high bit rates. …”
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