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Nano-scale TG-FinFET: Simulation and Analysis
Transistor has been designed and fabricated in the same way since its invention more than four decades ago enabling exponential shrinking in the channel length. However, hitting fundamental limits imposed the need for introducing disruptive technology to take over. FinFET - 3-D transistor - has been...
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| Format: | Thesis |
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AUC Knowledge Fountain
2016
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| _version_ | 1867613407685902336 |
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| access_status_str | Open Access |
| author | Youssef, Ahmed Taha Elthakeb Naguib |
| author_browse | Youssef, Ahmed Taha Elthakeb Naguib |
| author_facet | Youssef, Ahmed Taha Elthakeb Naguib |
| author_sort | Youssef, Ahmed Taha Elthakeb Naguib |
| collection | Thesis |
| dc_rights_str_mv | The author retains all rights with regard to copyright. The author certifies that written permission from the owner(s) of third-party copyrighted matter included in the thesis, dissertation, paper, or record of study has been obtained. The author further certifies that IRB approval has been obtained for this thesis, or that IRB approval is not necessary for this thesis. Insofar as this thesis, dissertation, paper, or record of study is an educational record as defined in the Family Educational Rights and Privacy Act (FERPA) (20 USC 1232g), the author has granted consent to disclosure of it to anyone who requests a copy. |
| description | Transistor has been designed and fabricated in the same way since its invention more than four decades ago enabling exponential shrinking in the channel length. However, hitting fundamental limits imposed the need for introducing disruptive technology to take over. FinFET - 3-D transistor - has been emerged as the first successor to MOSFET to continue the technology scaling roadmap. In this thesis, scaling of nano-meter FinFET has been investigated on both the device and circuit levels. The studies, primarily, consider FinFET in its tri-gate (TG) structure. On the device level, first, the main TCAD models used in simulating electron transport are benchmarked against the most accurate results on the semi-classical level using Monte Carlo techniques. Different models and modifications are investigated in a trial to extend one of the conventional models to the nano-scale simulations. Second, a numerical study for scaling TG-FinFET according to the most recent International Technology Roadmap of Semiconductors is carried out by means of quantum corrected 3-D Monte Carlo simulations in the ballistic and quasi-ballistic regimes, to assess its ultimate performance and scaling behavior for the next generations. Ballisticity ratio (BR) is extracted and discussed over different channel lengths. The electron velocity along the channel is analyzed showing the physical significance of the off-equilibrium transport with scaling the channel length. On the circuit level, first, the impact of FinFET scaling on basic circuit blocks is investigated based on the PTM models. 256-bit (6T) SRAM is evaluated for channel lengths of 20nm down to 7nm showing the scaling trends of basic performance metrics. In addition, the impact of VT variations on the delay, power, and stability is reported considering die-to-die variations. Second, we move to another peer-technology which is 28nm FD-SOI as a comparative study, keeping the SRAM cell as the test block, more advanced study is carried out considering the cell‘s stability and the evolution from dynamic to static metrics. |
| format | Thesis |
| id | oai:fount.aucegypt.edu:etds-1109 |
| institution | American University in Cairo (Egypt) |
| last_indexed | 2026-06-10T12:35:39.635Z |
| license_str | Other — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from AUC Knowledge Fountain — bepress |
| publishDate | 2016 |
| publishDateRange | 2016 |
| publishDateSort | 2016 |
| publisher | AUC Knowledge Fountain |
| publisherStr | AUC Knowledge Fountain |
| record_format | dspace |
| source_str | AUC Knowledge Fountain — bepress |
| spelling | oai:fount.aucegypt.edu:etds-1109 Nano-scale TG-FinFET: Simulation and Analysis Youssef, Ahmed Taha Elthakeb Naguib Transistor has been designed and fabricated in the same way since its invention more than four decades ago enabling exponential shrinking in the channel length. However, hitting fundamental limits imposed the need for introducing disruptive technology to take over. FinFET - 3-D transistor - has been emerged as the first successor to MOSFET to continue the technology scaling roadmap. In this thesis, scaling of nano-meter FinFET has been investigated on both the device and circuit levels. The studies, primarily, consider FinFET in its tri-gate (TG) structure. On the device level, first, the main TCAD models used in simulating electron transport are benchmarked against the most accurate results on the semi-classical level using Monte Carlo techniques. Different models and modifications are investigated in a trial to extend one of the conventional models to the nano-scale simulations. Second, a numerical study for scaling TG-FinFET according to the most recent International Technology Roadmap of Semiconductors is carried out by means of quantum corrected 3-D Monte Carlo simulations in the ballistic and quasi-ballistic regimes, to assess its ultimate performance and scaling behavior for the next generations. Ballisticity ratio (BR) is extracted and discussed over different channel lengths. The electron velocity along the channel is analyzed showing the physical significance of the off-equilibrium transport with scaling the channel length. On the circuit level, first, the impact of FinFET scaling on basic circuit blocks is investigated based on the PTM models. 256-bit (6T) SRAM is evaluated for channel lengths of 20nm down to 7nm showing the scaling trends of basic performance metrics. In addition, the impact of VT variations on the delay, power, and stability is reported considering die-to-die variations. Second, we move to another peer-technology which is 28nm FD-SOI as a comparative study, keeping the SRAM cell as the test block, more advanced study is carried out considering the cell‘s stability and the evolution from dynamic to static metrics. 2016-02-01T08:00:00Z thesis application/pdf https://fount.aucegypt.edu/etds/110 https://fount.aucegypt.edu/context/etds/article/1109/viewcontent/MS_20Thesis_20__20Ahmed_20T._20Elthakeb_20__202015_final.pdf The author retains all rights with regard to copyright. The author certifies that written permission from the owner(s) of third-party copyrighted matter included in the thesis, dissertation, paper, or record of study has been obtained. The author further certifies that IRB approval has been obtained for this thesis, or that IRB approval is not necessary for this thesis. Insofar as this thesis, dissertation, paper, or record of study is an educational record as defined in the Family Educational Rights and Privacy Act (FERPA) (20 USC 1232g), the author has granted consent to disclosure of it to anyone who requests a copy. Theses and Dissertations AUC Knowledge Fountain FinFET Tri-Gate Transistor |
| spellingShingle | FinFET Tri-Gate Transistor Youssef, Ahmed Taha Elthakeb Naguib Nano-scale TG-FinFET: Simulation and Analysis |
| title | Nano-scale TG-FinFET: Simulation and Analysis |
| title_full | Nano-scale TG-FinFET: Simulation and Analysis |
| title_fullStr | Nano-scale TG-FinFET: Simulation and Analysis |
| title_full_unstemmed | Nano-scale TG-FinFET: Simulation and Analysis |
| title_short | Nano-scale TG-FinFET: Simulation and Analysis |
| title_sort | nano scale tg finfet simulation and analysis |
| topic | FinFET Tri-Gate Transistor |
| url | https://fount.aucegypt.edu/etds/110 https://fount.aucegypt.edu/context/etds/article/1109/viewcontent/MS_20Thesis_20__20Ahmed_20T._20Elthakeb_20__202015_final.pdf |
| work_keys_str_mv | AT youssefahmedtahaelthakebnaguib nanoscaletgfinfetsimulationandanalysis |