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ON sectored sensor to actuator networked control systems architectures with fault tolerance at the sensor level
Networked Control Systems are broadly implemented to meet the demands of many critical industrial applications. This study proposes an NCS system that employs Sectoring to a Sensor to Actuator (S2A) architecture. The proposed system guarantees no over delayed packets with zero packet loss using Giga...
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| Format: | Thesis |
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AUC Knowledge Fountain
2019
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| Summary: | Networked Control Systems are broadly implemented to meet the demands of many critical industrial applications. This study proposes an NCS system that employs Sectoring to a Sensor to Actuator (S2A) architecture. The proposed system guarantees no over delayed packets with zero packet loss using Gigabit Ethernet, and this is accomplished using Riverbed Modeler simulations. Hence, succeeding in meeting all the required real-time constraints. System performance is then compared quantitatively to the in-loop and the S2A NCS models. Moreover, Sift-out modular redundancy is implemented at the sensor level. It is evident that the system can sustain the extra network load with no violations to the control deadline and with zero packet loss. To compare the system reliability after the applied redundancy, a case study is conducted to justify the extra cost of the added sift-out system. Furthermore, the study considered the issue that might arise with the increased number of cabling in the sift-out system and considered that it might decrease the overall system reliability. Hence. An FPGA-based fault tolerant system is proposed to decrease the number of cables in the system and enhance the overall system reliability. The fault model in this study considered Single Event Upsets and hard failures. A reliability analysis is thus conducted to evaluate the reliability of each block in the system and then the overall system reliability. Finally, a generic reliability analysis is presented to explore the flexibility of the fault tolerant system, and a case study is shown to demonstrate the enhancement in reliability over the system that did not implement the FPGA solution and resulting cable reduction. |
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