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A programmable receiver front-end for multi-band/multi-standard applications
Nowadays, wireless communication devices need a compact wireless receiver, so that it can access all the available services at any time and at any location with minimum power consumption and compact area. The desire for covering all the service specifications tremendously increases the demand for mu...
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| Format: | Thesis |
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AUC Knowledge Fountain
2015
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| Summary: | Nowadays, wireless communication devices need a compact wireless receiver, so that it can access all the available services at any time and at any location with minimum power consumption and compact area. The desire for covering all the service specifications tremendously increases the demand for multi-band/multi-standard wireless receivers. A reconfigurable receiver comes to give a hand. In this work, a universal programmable multi-band multi-standard receiver using CMOS technology is proposed. The receiver aims to target LTE specifications on the frequency range (700MHz-2.4GHz) as a case study to prove the concept of supporting multi-bands. The receiver is tested over three different frequencies 500MHz, 1GHz and 2GHz to prove its programmability. Sampling receivers and impedance translation technique are the main factors to approach the desired programmable receiver front-end. The receiver uses a quadrature band-pass charge sampling filter programmed via its controlling clocks. It forms the signal path which selects the signal, down-converts it to IF frequency and subsamples the signal decreasing the sampling frequency of the proceeding ADC. By adjusting the controlling clocks of the switches, the filter center frequency is maintained at the desired frequency. A time varying matching network based on impedance translation technique is used for multi-frequencies matching and further selectivity enhancing the receiver’s linearity. The receiver front-end architecture achieves a NF of (7: 9) dB, a gain of (23: 28) dB, an out-of-band IIP3 of (-1.9 : -5.5) dBm and an in-band IIP3 of (-1.9 : -5.7) dBm across the tested frequencies. The design is tested across process corners. The layout of the design occupies 0.45mm2. The design is tested post layout to prove its reliability. |
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