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Modeling the phase step response of digital Bang-Bang PLLs
Bang-Bang Phase Locked Loops (BB-PLLs) are a class of phase locked loops that incorporate binary phase detectors. BB-PLLs offer a low power implementation of PLLs at the cost of nonlinear loop dynamics. Since low power design is currently one of the most significant research areas in the field of VL...
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2013
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| _version_ | 1867613419156275200 |
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| access_status_str | Open Access |
| author | Abdelfattah, Moataz |
| author_browse | Abdelfattah, Moataz |
| author_facet | Abdelfattah, Moataz |
| author_sort | Abdelfattah, Moataz |
| collection | Thesis |
| dc_rights_str_mv | The author retains all rights with regard to copyright. The author certifies that written permission from the owner(s) of third-party copyrighted matter included in the thesis, dissertation, paper, or record of study has been obtained. The author further certifies that IRB approval has been obtained for this thesis, or that IRB approval is not necessary for this thesis. Insofar as this thesis, dissertation, paper, or record of study is an educational record as defined in the Family Educational Rights and Privacy Act (FERPA) (20 USC 1232g), the author has granted consent to disclosure of it to anyone who requests a copy. The author has granted the American University in Cairo or its agents a non-exclusive license to archive this thesis, dissertation, paper, or record of study, and to make it accessible, in whole or in part, in all forms of media, now or hereafter known. |
| description | Bang-Bang Phase Locked Loops (BB-PLLs) are a class of phase locked loops that incorporate binary phase detectors. BB-PLLs offer a low power implementation of PLLs at the cost of nonlinear loop dynamics. Since low power design is currently one of the most significant research areas in the field of VLSI, BB-PLLs have recently gained an increasing interest in the VLSI research communities. Moreover, BB-PLLs can be easily implemented using digital circuits, and thus, enable seamless scaling across technology nodes. The nonlinearity of the BB-PLLs, however, results in a number of problems associated with the design of BB-PLLs. One of the main problems of BB-PLLs is the difficulty in modeling the nonlinear system, which leads to the lack of a well-defined design methodology. Another problem of BB-PLLs is that the response of the system depends on the Phase Error Magnitude (PEM), and thus, the system does not have a constant Bandwidth (BW). These problems make the BB-PLLs undesirable for many applications. The main focus of this work is to develop a generic modeling methodology that can be applied to any Digital BB-PLL to predict the response of the BB-PLL prior to starting the circuit design. The benefit of this modeling methodology is to define a design methodology for BB-PLLs, and to facilitate the design process. In order to verify the proposed model, a conventional Digital BB-PLL is implemented on the circuit level, and VI compared to the model. Moreover, the insights gained by the model are used to propose techniques that can be used to enhance the system linearity. Verified by AMS simulations, the model is proved to be successful in predicting the system response. Furthermore, the proposed techniques are compared to the conventional system. Simulations demonstrated that the impact of the proposed techniques is about 35% enhancement in the system linearity, and 55% reduction in the settling time of the phase step response. |
| format | Thesis |
| id | oai:fount.aucegypt.edu:etds-2590 |
| institution | American University in Cairo (Egypt) |
| last_indexed | 2026-06-10T12:35:50.652Z |
| license_str | Other — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from AUC Knowledge Fountain — bepress |
| publishDate | 2013 |
| publishDateRange | 2013 |
| publishDateSort | 2013 |
| publisher | AUC Knowledge Fountain |
| publisherStr | AUC Knowledge Fountain |
| record_format | dspace |
| source_str | AUC Knowledge Fountain — bepress |
| spelling | oai:fount.aucegypt.edu:etds-2590 Modeling the phase step response of digital Bang-Bang PLLs Abdelfattah, Moataz Bang-Bang Phase Locked Loops (BB-PLLs) are a class of phase locked loops that incorporate binary phase detectors. BB-PLLs offer a low power implementation of PLLs at the cost of nonlinear loop dynamics. Since low power design is currently one of the most significant research areas in the field of VLSI, BB-PLLs have recently gained an increasing interest in the VLSI research communities. Moreover, BB-PLLs can be easily implemented using digital circuits, and thus, enable seamless scaling across technology nodes. The nonlinearity of the BB-PLLs, however, results in a number of problems associated with the design of BB-PLLs. One of the main problems of BB-PLLs is the difficulty in modeling the nonlinear system, which leads to the lack of a well-defined design methodology. Another problem of BB-PLLs is that the response of the system depends on the Phase Error Magnitude (PEM), and thus, the system does not have a constant Bandwidth (BW). These problems make the BB-PLLs undesirable for many applications. The main focus of this work is to develop a generic modeling methodology that can be applied to any Digital BB-PLL to predict the response of the BB-PLL prior to starting the circuit design. The benefit of this modeling methodology is to define a design methodology for BB-PLLs, and to facilitate the design process. In order to verify the proposed model, a conventional Digital BB-PLL is implemented on the circuit level, and VI compared to the model. Moreover, the insights gained by the model are used to propose techniques that can be used to enhance the system linearity. Verified by AMS simulations, the model is proved to be successful in predicting the system response. Furthermore, the proposed techniques are compared to the conventional system. Simulations demonstrated that the impact of the proposed techniques is about 35% enhancement in the system linearity, and 55% reduction in the settling time of the phase step response. 2013-02-27T08:00:00Z thesis application/pdf https://fount.aucegypt.edu/etds/1554 https://fount.aucegypt.edu/context/etds/article/2590/viewcontent/auto_convert.pdf The author retains all rights with regard to copyright. The author certifies that written permission from the owner(s) of third-party copyrighted matter included in the thesis, dissertation, paper, or record of study has been obtained. The author further certifies that IRB approval has been obtained for this thesis, or that IRB approval is not necessary for this thesis. Insofar as this thesis, dissertation, paper, or record of study is an educational record as defined in the Family Educational Rights and Privacy Act (FERPA) (20 USC 1232g), the author has granted consent to disclosure of it to anyone who requests a copy. The author has granted the American University in Cairo or its agents a non-exclusive license to archive this thesis, dissertation, paper, or record of study, and to make it accessible, in whole or in part, in all forms of media, now or hereafter known. Theses and Dissertations AUC Knowledge Fountain Electronic circuit design Phase-locked loops |
| spellingShingle | Electronic circuit design Phase-locked loops Abdelfattah, Moataz Modeling the phase step response of digital Bang-Bang PLLs |
| title | Modeling the phase step response of digital Bang-Bang PLLs |
| title_full | Modeling the phase step response of digital Bang-Bang PLLs |
| title_fullStr | Modeling the phase step response of digital Bang-Bang PLLs |
| title_full_unstemmed | Modeling the phase step response of digital Bang-Bang PLLs |
| title_short | Modeling the phase step response of digital Bang-Bang PLLs |
| title_sort | modeling the phase step response of digital bang bang plls |
| topic | Electronic circuit design Phase-locked loops |
| url | https://fount.aucegypt.edu/etds/1554 https://fount.aucegypt.edu/context/etds/article/2590/viewcontent/auto_convert.pdf |
| work_keys_str_mv | AT abdelfattahmoataz modelingthephasestepresponseofdigitalbangbangplls |