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Minimisation of Test Application time in the scan technique
A Thesis submitted to the Department of Telecommunication Engineering, Kwame Nkrumah University of Science and Technology in partial ful lment of the requirements for the degree of Master of Science
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| Format: | Article |
| Language: | English |
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2011
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| _version_ | 1867613137034805248 |
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| access_status_str | Open Access |
| author | Opare Adu-Boahen, Kwasi |
| author_browse | Opare Adu-Boahen, Kwasi |
| author_facet | Opare Adu-Boahen, Kwasi |
| author_sort | Opare Adu-Boahen, Kwasi |
| collection | Thesis |
| description | A Thesis submitted to the Department of Telecommunication
Engineering, Kwame Nkrumah University of Science and Technology in partial ful lment of the requirements for the degree of Master of Science |
| format | Article |
| id | oai:ir.knust.edu.gh:123456789/364 |
| institution | KNUST (Ghana) |
| language | English |
| last_indexed | 2026-06-10T12:31:21.331Z |
| license_str | Not specified — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from KNUSTSpace — Kwame Nkrumah University of Science & Technology (Ghana) |
| publishDate | 2011 |
| publishDateRange | 2011 |
| publishDateSort | 2011 |
| record_format | dspace |
| source_str | KNUSTSpace — Kwame Nkrumah University of Science & Technology (Ghana) |
| spelling | oai:ir.knust.edu.gh:123456789/364 Minimisation of Test Application time in the scan technique Opare Adu-Boahen, Kwasi A Thesis submitted to the Department of Telecommunication Engineering, Kwame Nkrumah University of Science and Technology in partial ful lment of the requirements for the degree of Master of Science The focus of this study is on how test application time in the scan technique can be minimised. A novel method of how this can be achieved, called the Vector Match Approach, is presented. It takes advantage of matching patterns in test vectors, by rearranging them such that those with matching patterns are closer to each other. Flow charts describing the logic of the algorithm and an example, illustrating how it works are also shown. In addition, the circuit architecture for the Vector Match Approach is presented. It incorporates a scan register and a multiple-input signature register (MISR) together with the circuit under test. 2011-07-15T14:53:06Z 2023-04-20T02:50:18Z 2010-07-15T14:53:06Z 2023-04-20T02:50:18Z January, 2010 Article https://ir.knust.edu.gh/handle/123456789/364 en application/pdf |
| spellingShingle | Opare Adu-Boahen, Kwasi Minimisation of Test Application time in the scan technique |
| title | Minimisation of Test Application time in the scan technique |
| title_full | Minimisation of Test Application time in the scan technique |
| title_fullStr | Minimisation of Test Application time in the scan technique |
| title_full_unstemmed | Minimisation of Test Application time in the scan technique |
| title_short | Minimisation of Test Application time in the scan technique |
| title_sort | minimisation of test application time in the scan technique |
| url | https://ir.knust.edu.gh/handle/123456789/364 |
| work_keys_str_mv | AT opareaduboahenkwasi minimisationoftestapplicationtimeinthescantechnique |