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An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline
Includes bibliographical references.
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| Main Author: | |
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| Other Authors: | |
| Format: | Thesis |
| Language: | English |
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Department of Electrical Engineering
2015
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| _version_ | 1867614063956066304 |
|---|---|
| access_status_str | Open Access |
| author | Wyngaard, Janet Ruth |
| author2 | Inggs, Michael |
| author_browse | Inggs, Michael Wyngaard, Janet Ruth |
| author_facet | Inggs, Michael Wyngaard, Janet Ruth |
| author_sort | Wyngaard, Janet Ruth |
| collection | Thesis |
| description | Includes bibliographical references. |
| format | Thesis |
| id | oai:open.uct.ac.za:11427/13265 |
| institution | University of Cape Town (South Africa) |
| language | eng |
| last_indexed | 2026-06-10T12:46:05.754Z |
| license_str | Not specified — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from UCTD — University of Cape Town Open Access Repository |
| publishDate | 2015 |
| publishDateRange | 2015 |
| publishDateSort | 2015 |
| publisher | Department of Electrical Engineering |
| publisherStr | Department of Electrical Engineering |
| record_format | dspace |
| source_str | UCTD — University of Cape Town Open Access Repository |
| spelling | oai:open.uct.ac.za:11427/13265 An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline Wyngaard, Janet Ruth Inggs, Michael Collins, J Electrical Engineering Includes bibliographical references. In light of the power, memory, ILP, and utilisation walls facing the computing industry, this work examines the hypothetical many-core approach to finding greater compute performance and efficiency. In order to achieve greater efficiency in an environment in which Moore’s law continues but TDP has been capped, a means of deriving performance from dark and dim silicon is needed. The many-core hypothesis is one approach to exploiting these available transistors efficiently. As understood in this work, it involves trading in hardware control complexity for hundreds to thousands of parallel simple processing elements, and operating at a clock speed sufficiently low as to allow the efficiency gains of near threshold voltage operation. Performance is there- fore dependant on exploiting a new degree of fine-grained parallelism such as is currently only found in GPGPUs, but in a manner that is not as restrictive in application domain range. While removing the complex control hardware of traditional CPUs provides space for more arithmetic hardware, a basic level of control is still required. For a number of reasons this work chooses to replace this control largely with static scheduling. This pushes the burden of control primarily to the software and specifically the compiler, rather not to the programmer or to an application specific means of control simplification. An existing legacy tool chain capable of autoparallelising sequential Fortran code to the degree of parallelism necessary for many-core exists. This work implements a many-core architecture to match it. Prototyping the design on an FPGA, it is possible to examine the real world performance of the compiler-architecture system to a greater degree than simulation only would allow. Comparing theoretical peak performance and real performance in a case study application, the system is found to be more efficient than any other reviewed, but to also significantly under perform relative to current competing architectures. This failing is apportioned to taking the need for simple hardware too far, and an inability to implement static scheduling mitigating tactics due to lack of support for such in the compiler. 2015-07-02T08:28:20Z 2015-07-02T08:28:20Z 2014 Doctoral Thesis Doctoral PhD http://hdl.handle.net/11427/13265 eng application/pdf Department of Electrical Engineering Faculty of Engineering and the Built Environment University of Cape Town |
| spellingShingle | Electrical Engineering Wyngaard, Janet Ruth An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline |
| thesis_degree_str | Doctoral |
| title | An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline |
| title_full | An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline |
| title_fullStr | An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline |
| title_full_unstemmed | An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline |
| title_short | An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline |
| title_sort | fpga implementation of an investigative many core processor fynbos in support of a fortran autoparallelising software pipeline |
| topic | Electrical Engineering |
| url | http://hdl.handle.net/11427/13265 |
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