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RHINO software-defined radio processing blocks
This MSc project focuses on the design and implementation of a library of parameterizable, modular and reusable Digital IP blocks designed around use in Software-Defined Radio (SDR) applications and compatibility with the RHINO platform. The RHINO platform has commonalities with the better known ROA...
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| Format: | Thesis |
| Language: | English |
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Department of Electrical Engineering
2016
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| _version_ | 1867614254468694016 |
|---|---|
| access_status_str | Open Access |
| author | Tsoeunyane, Lekhobola Joachim |
| author2 | Winberg, Simon |
| author_browse | Tsoeunyane, Lekhobola Joachim Winberg, Simon |
| author_facet | Winberg, Simon Tsoeunyane, Lekhobola Joachim |
| author_sort | Tsoeunyane, Lekhobola Joachim |
| collection | Thesis |
| description | This MSc project focuses on the design and implementation of a library of parameterizable, modular and reusable Digital IP blocks designed around use in Software-Defined Radio (SDR) applications and compatibility with the RHINO platform. The RHINO platform has commonalities with the better known ROACH platform, but it is a significantly cut-down and lowercost alternative which has similarities in the interfacing and FPGA/Processor interconnects of ROACH. The purpose of the library and design framework presented in this work aims to alleviate some of the commercial, high cost and static structure concerns about IP cores provided by FPGA manufactures and third-party IP vendors. It will also work around the lack of parameters and bus compatibility issues often encountered when using the freely available open resources. The RHINO hardware platform will be used for running practical applications and testing of the blocks. The HDL library that is being constructed is targeted towards both novice and experienced low-level HDL developers who can download and use it for free, and it will provide them experience of using IP Cores that support open bus interfaces in order to exploit SoC design without commercial, parameter and bus compatibility limitations. The provided modules will be of particularly benefit to the novice developers in providing ready-made examples of processing blocks, as well as parameterization settings for the interfacing blocks and associated RF receiver side configuration settings; all together these examples will help new developers establish effective ways to build their own SDR prototypes using RHINO. |
| format | Thesis |
| id | oai:open.uct.ac.za:11427/20102 |
| institution | University of Cape Town (South Africa) |
| language | eng |
| last_indexed | 2026-06-10T12:49:07.441Z |
| license_str | Not specified — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from UCTD — University of Cape Town Open Access Repository |
| publishDate | 2016 |
| publishDateRange | 2016 |
| publishDateSort | 2016 |
| publisher | Department of Electrical Engineering |
| publisherStr | Department of Electrical Engineering |
| record_format | dspace |
| source_str | UCTD — University of Cape Town Open Access Repository |
| spelling | oai:open.uct.ac.za:11427/20102 RHINO software-defined radio processing blocks Tsoeunyane, Lekhobola Joachim Winberg, Simon Inggs, Michael Electrical Engineering This MSc project focuses on the design and implementation of a library of parameterizable, modular and reusable Digital IP blocks designed around use in Software-Defined Radio (SDR) applications and compatibility with the RHINO platform. The RHINO platform has commonalities with the better known ROACH platform, but it is a significantly cut-down and lowercost alternative which has similarities in the interfacing and FPGA/Processor interconnects of ROACH. The purpose of the library and design framework presented in this work aims to alleviate some of the commercial, high cost and static structure concerns about IP cores provided by FPGA manufactures and third-party IP vendors. It will also work around the lack of parameters and bus compatibility issues often encountered when using the freely available open resources. The RHINO hardware platform will be used for running practical applications and testing of the blocks. The HDL library that is being constructed is targeted towards both novice and experienced low-level HDL developers who can download and use it for free, and it will provide them experience of using IP Cores that support open bus interfaces in order to exploit SoC design without commercial, parameter and bus compatibility limitations. The provided modules will be of particularly benefit to the novice developers in providing ready-made examples of processing blocks, as well as parameterization settings for the interfacing blocks and associated RF receiver side configuration settings; all together these examples will help new developers establish effective ways to build their own SDR prototypes using RHINO. 2016-06-23T14:50:09Z 2016-06-23T14:50:09Z 2015 Master Thesis Masters MSc (Eng) http://hdl.handle.net/11427/20102 eng application/pdf Department of Electrical Engineering Faculty of Engineering and the Built Environment University of Cape Town |
| spellingShingle | Electrical Engineering Tsoeunyane, Lekhobola Joachim RHINO software-defined radio processing blocks |
| thesis_degree_str | Master's |
| title | RHINO software-defined radio processing blocks |
| title_full | RHINO software-defined radio processing blocks |
| title_fullStr | RHINO software-defined radio processing blocks |
| title_full_unstemmed | RHINO software-defined radio processing blocks |
| title_short | RHINO software-defined radio processing blocks |
| title_sort | rhino software defined radio processing blocks |
| topic | Electrical Engineering |
| url | http://hdl.handle.net/11427/20102 |
| work_keys_str_mv | AT tsoeunyanelekhobolajoachim rhinosoftwaredefinedradioprocessingblocks |