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A hardware implementation of a Viterbi decoder for a (3,2/3) TCM code
The report details the design of a dedicated Viterbi decoder chip set for an Ungerboek (3,2/3) Trellis Coded Modulation code. It was the specific intention of the thesis to design a system that could be implemented on standard Field Programmable Gate Arrays (FPGA) yet still be able to cope with high...
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| Format: | Thesis |
| Language: | English |
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Department of Electrical Engineering
2016
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