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Python based FPGA design-flow
This dissertation undertakes to establish the feasibility of using MyHDL as a basis on which to develop an FPGA-based DSP tool-ow to target CASPER hardware. MyHDL is an open-source package which enables Python to be used as a hardware definition and verification language. As Python is a high-level l...
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| Format: | Thesis |
| Language: | English |
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Department of Electrical Engineering
2016
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| _version_ | 1867614380760236032 |
|---|---|
| access_status_str | Open Access |
| author | New, Wesley |
| author2 | Inggs, Michael |
| author_browse | Inggs, Michael New, Wesley |
| author_facet | Inggs, Michael New, Wesley |
| author_sort | New, Wesley |
| collection | Thesis |
| description | This dissertation undertakes to establish the feasibility of using MyHDL as a basis on which to develop an FPGA-based DSP tool-ow to target CASPER hardware. MyHDL is an open-source package which enables Python to be used as a hardware definition and verification language. As Python is a high-level language, hardware designers can use it to model and simulate designs, without needing detailed knowledge of the underlying hardware. MyHDL has the ability to convert designs to Verilog or VHDL allowing it to integrate into the more traditional design-ow. The CASPER tool- ow exhibits limitations such as design environment instability and high licensing fees. These shortcomings are addressed by MyHDL. To enable CASPER to take advantage of its powerful features, MyHDL is incorporated into a next generation tool-ow which enables high-level designs to be fully simulated and implemented on the CASPER hardware architectures. |
| format | Thesis |
| id | oai:open.uct.ac.za:11427/20339 |
| institution | University of Cape Town (South Africa) |
| language | eng |
| last_indexed | 2026-06-10T12:51:07.882Z |
| license_str | Not specified — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from UCTD — University of Cape Town Open Access Repository |
| publishDate | 2016 |
| publishDateRange | 2016 |
| publishDateSort | 2016 |
| publisher | Department of Electrical Engineering |
| publisherStr | Department of Electrical Engineering |
| record_format | dspace |
| source_str | UCTD — University of Cape Town Open Access Repository |
| spelling | oai:open.uct.ac.za:11427/20339 Python based FPGA design-flow New, Wesley Inggs, Michael Winberg, Simon Electrical Engineering Software Programming Languages - Python This dissertation undertakes to establish the feasibility of using MyHDL as a basis on which to develop an FPGA-based DSP tool-ow to target CASPER hardware. MyHDL is an open-source package which enables Python to be used as a hardware definition and verification language. As Python is a high-level language, hardware designers can use it to model and simulate designs, without needing detailed knowledge of the underlying hardware. MyHDL has the ability to convert designs to Verilog or VHDL allowing it to integrate into the more traditional design-ow. The CASPER tool- ow exhibits limitations such as design environment instability and high licensing fees. These shortcomings are addressed by MyHDL. To enable CASPER to take advantage of its powerful features, MyHDL is incorporated into a next generation tool-ow which enables high-level designs to be fully simulated and implemented on the CASPER hardware architectures. 2016-07-14T12:17:25Z 2016-07-14T12:17:25Z 2016 Master Thesis Masters MSc (Eng) http://hdl.handle.net/11427/20339 eng application/pdf Department of Electrical Engineering Faculty of Engineering and the Built Environment University of Cape Town |
| spellingShingle | Electrical Engineering Software Programming Languages - Python New, Wesley Python based FPGA design-flow |
| thesis_degree_str | Master's |
| title | Python based FPGA design-flow |
| title_full | Python based FPGA design-flow |
| title_fullStr | Python based FPGA design-flow |
| title_full_unstemmed | Python based FPGA design-flow |
| title_short | Python based FPGA design-flow |
| title_sort | python based fpga design flow |
| topic | Electrical Engineering Software Programming Languages - Python |
| url | http://hdl.handle.net/11427/20339 |
| work_keys_str_mv | AT newwesley pythonbasedfpgadesignflow |