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Architectural Level Computational Hardware Abstraction: A New Programming Language for FPGA Projects
Recent years have seen vast improvements to the capability of programmable processing platforms, especially field programmable gate arrays, or FPGAs. Modern software languages have been developed, adding features such as duck-typing, dynamic interpretation, built-in high level data structures, etc....
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| Format: | Thesis |
| Language: | English |
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Department of Electrical Engineering
2023
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| Summary: | Recent years have seen vast improvements to the capability of programmable processing platforms, especially field programmable gate arrays, or FPGAs. Modern software languages have been developed, adding features such as duck-typing, dynamic interpretation, built-in high level data structures, etc. Yet, FPGA development is still mostly using traditional hardware description languages such as VHDL and Verilog, and the industry is resorting to third party tools and scripting-based automation in order to increase developer efficiency. This dissertation presents ALCHA: a new object-oriented language aimed at low-level FPGA development. Main language objectives include increasing the architectural abstraction capabilities, introducing structured programming to FPGA development, automating fixed-point related design, integrating design constraints and increasing the generalisation capability. In short, the ALCHA language is designed to allow the user to increase abstraction and reduce maintenance effort. After ensuring that the language grammar is parsable, the resulting language design is evaluated by means of a radar-based case study. Language complexity measurement is based on the number of lines of code, and language power is based on the cost of maintenance. ALCHA is shown to support code that is about half as complex and twice as powerful as traditional HDL-based design, based on these metrics. In future, ALCHA could evolve into a hardware description language in its own right, allowing developers to leverage the strengths of FPGAs. |
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