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Development of a parallel SAR processor on a Beowulf cluster
Includes bibliographical references.
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| Main Author: | |
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| Other Authors: | |
| Format: | Thesis |
| Language: | English |
| Published: |
Department of Electrical Engineering
2014
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| _version_ | 1867613257114583042 |
|---|---|
| access_status_str | Open Access |
| author | Bennett, Thomas Gerald Hart |
| author2 | Inggs, Michael |
| author_browse | Bennett, Thomas Gerald Hart Inggs, Michael |
| author_facet | Inggs, Michael Bennett, Thomas Gerald Hart |
| author_sort | Bennett, Thomas Gerald Hart |
| collection | Thesis |
| description | Includes bibliographical references. |
| format | Thesis |
| id | oai:open.uct.ac.za:11427/5247 |
| institution | University of Cape Town (South Africa) |
| language | eng |
| last_indexed | 2026-06-10T12:33:15.376Z |
| license_str | Not specified — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from UCTD — University of Cape Town Open Access Repository |
| publishDate | 2014 |
| publishDateRange | 2014 |
| publishDateSort | 2014 |
| publisher | Department of Electrical Engineering |
| publisherStr | Department of Electrical Engineering |
| record_format | dspace |
| source_str | UCTD — University of Cape Town Open Access Repository |
| spelling | oai:open.uct.ac.za:11427/5247 Development of a parallel SAR processor on a Beowulf cluster Bennett, Thomas Gerald Hart Inggs, Michael Electrical Engineering Includes bibliographical references. The purpose of this dissertation is to present the development and testing of the parallelisation of a Range-Doppler SAR processor. The inherent data parallelism found in SAR data lead to the choice of using master slave parallel processor, where copies of a slave task perform the same tasks on different sets of data. However, the SAR processor that was parallelised needed to implement a corner turn without saving data to disk keeping the data set being processed distributed in memory over the nodes in the cluster. This was successfully achieved using a in-place method, thus saving valuable memory resources. Once the parallel processor was implemented some timing tests were performed, yielding a maximum speedup factor of 6.2 for an 8 slave processor system. 2014-07-31T11:00:15Z 2014-07-31T11:00:15Z 2003 Master Thesis Masters MSc http://hdl.handle.net/11427/5247 eng application/pdf Department of Electrical Engineering Faculty of Engineering and the Built Environment University of Cape Town |
| spellingShingle | Electrical Engineering Bennett, Thomas Gerald Hart Development of a parallel SAR processor on a Beowulf cluster |
| thesis_degree_str | Master's |
| title | Development of a parallel SAR processor on a Beowulf cluster |
| title_full | Development of a parallel SAR processor on a Beowulf cluster |
| title_fullStr | Development of a parallel SAR processor on a Beowulf cluster |
| title_full_unstemmed | Development of a parallel SAR processor on a Beowulf cluster |
| title_short | Development of a parallel SAR processor on a Beowulf cluster |
| title_sort | development of a parallel sar processor on a beowulf cluster |
| topic | Electrical Engineering |
| url | http://hdl.handle.net/11427/5247 |
| work_keys_str_mv | AT bennettthomasgeraldhart developmentofaparallelsarprocessoronabeowulfcluster |