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Feasibility of CMOS optical clock distribution networks
Dissertation (MEng)--University of Pretoria, 2009.
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University of Pretoria
2013
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| _version_ | 1867613592572919808 |
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| access_status_str | Open Access |
| author2 | Du Plessis, Monuko |
| author_browse | Du Plessis, Monuko |
| author_facet | Du Plessis, Monuko |
| collection | Thesis |
| dc_rights_str_mv | © 2009, University of Pretoria. All rights reserved. The copyright in this work vests in the University of Pretoria. No part of this work may be reproduced or transmitted in any form or by any means, without the prior written permission of the University of Pretoria. |
| description | Dissertation (MEng)--University of Pretoria, 2009. |
| format | Thesis |
| id | oai:repository.up.ac.za:2263/26440 |
| institution | University of Pretoria (South Africa) |
| last_indexed | 2026-06-10T12:38:35.948Z |
| license_str | Other — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from UPSpace — University of Pretoria Institutional Repository |
| publishDate | 2013 |
| publishDateRange | 2013 |
| publishDateSort | 2013 |
| publisher | University of Pretoria |
| publisherStr | University of Pretoria |
| record_format | dspace |
| source_str | UPSpace — University of Pretoria Institutional Repository |
| spelling | oai:repository.up.ac.za:2263/26440 Feasibility of CMOS optical clock distribution networks Du Plessis, Monuko jannes.venter@up.ac.za Venter, Petrus Johannes Clock disribution Cmos Optical clock Optical interconnect Repeater H-tree Detection Power consumption UCTD Dissertation (MEng)--University of Pretoria, 2009. CMOS is well known for its ability to scale. This fact is reflected in the aggressive scaling on a continual basis from the invention of CMOS up to date. As devices are scaled, device performance improves due to shorter channel lengths and more densely packed functions for the same amount of area. In recent years, however, the performance gain obtained through scaling has begun to suffer under the degradation of the associate interconnect performance. As devices become smaller, interconnects need to follow. Unlike transistors, the scaling of interconnects results in higher capacitances and resistances, thereby limiting overall system performance. Trying to alleviate the delay effects results in increased power consumption, especially in global structures such as clock distribution networks. A possible solution to this problem is the use of optical interconnects, which are fast and much less lossy than the electrical equivalents. This dissertation describes an investigation on what future technology nodes will entail in terms of power consumption of clock networks, and what is required for an optical alternative to become feasible. A common clock configuration is used as a basis for comparison, where both electrical and optical networks are designed to component level. Optimisation is done on both to ensure a reasonable comparison, and the results of the respective power consumption components are then compared in order to find the criteria for a feasible optical clock distribution scheme. Copyright Electrical, Electronic and Computer Engineering unrestricted 2013-09-07T05:33:26Z 2010-07-21 2013-09-07T05:33:26Z 2010-05-27 2009 2010-07-20 Dissertation Venter, PJ 2009, Feasibility of CMOS optical clock distribution networks, MEng dissertation, University of Pretoria, Pretoria, viewed yymmdd < http://hdl.handle.net/2263/26440 > C10/459/gm http://hdl.handle.net/2263/26440 http://upetd.up.ac.za/thesis/available/etd-07202010-194604/ © 2009, University of Pretoria. All rights reserved. The copyright in this work vests in the University of Pretoria. No part of this work may be reproduced or transmitted in any form or by any means, without the prior written permission of the University of Pretoria. application/pdf University of Pretoria |
| spellingShingle | Clock disribution Cmos Optical clock Optical interconnect Repeater H-tree Detection Power consumption UCTD Feasibility of CMOS optical clock distribution networks |
| title | Feasibility of CMOS optical clock distribution networks |
| title_full | Feasibility of CMOS optical clock distribution networks |
| title_fullStr | Feasibility of CMOS optical clock distribution networks |
| title_full_unstemmed | Feasibility of CMOS optical clock distribution networks |
| title_short | Feasibility of CMOS optical clock distribution networks |
| title_sort | feasibility of cmos optical clock distribution networks |
| topic | Clock disribution Cmos Optical clock Optical interconnect Repeater H-tree Detection Power consumption UCTD |
| url | http://hdl.handle.net/2263/26440 http://upetd.up.ac.za/thesis/available/etd-07202010-194604/ |