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Low phase noise 2 GHz Fractional-N CMOS synthesizer IC
Dissertation (MEng)--University of Pretoria, 2010.
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| Format: | Thesis |
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University of Pretoria
2013
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| _version_ | 1867613502298914816 |
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| access_status_str | Open Access |
| author2 | Sinha, Saurabh |
| author_browse | Sinha, Saurabh |
| author_facet | Sinha, Saurabh |
| collection | Thesis |
| dc_rights_str_mv | © 2010, University of Pretoria. All rights reserved. The copyright in this work vests in the University of Pretoria. No part of this work may be reproduced or transmitted in any form or by any means, without the prior written permission of the University of Pretoria. |
| description | Dissertation (MEng)--University of Pretoria, 2010. |
| format | Thesis |
| id | oai:repository.up.ac.za:2263/27921 |
| institution | University of Pretoria (South Africa) |
| last_indexed | 2026-06-10T12:37:10.039Z |
| license_str | Other — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from UPSpace — University of Pretoria Institutional Repository |
| publishDate | 2013 |
| publishDateRange | 2013 |
| publishDateSort | 2013 |
| publisher | University of Pretoria |
| publisherStr | University of Pretoria |
| record_format | dspace |
| source_str | UPSpace — University of Pretoria Institutional Repository |
| spelling | oai:repository.up.ac.za:2263/27921 Low phase noise 2 GHz Fractional-N CMOS synthesizer IC Sinha, Saurabh gert.veale@gmail.com Veale, Gerhardus Ignatius Potgieter Cml-to-cmos converter Cml flicker noise Fractional-n Cmos pfd Cml pfd Cml 4-bit counter Cml Cml 2/3-prescaler Ssb phase noise Pulse-swallow counter Low division Programmable modulus accumulator High voltage charge-pump In-band phase noise UCTD Dissertation (MEng)--University of Pretoria, 2010. Low noise low division 2 GHz RF synthesizer integrated circuits (ICs) are conventionally implemented in some form of HBT process such as SiGe or GaAs. The research in this dissertation differs from convention, with the aim of implementing a synthesizer IC in a more convenient, low-cost Si-based CMOS process. A collection of techniques to push towards the noise and frequency limits of CMOS processes, and possibly other IC processes, is then one of the research outcomes. In a synthesizer low N-divider ratios are important, as high division ratios would amplify in-band phase noise. The design methods deployed as part of this research achieve low division ratios (4 ≤ N ≤ 33) and a high phase comparison frequency (>100 MHz). The synthesizer IC employs a first-order fractional-N topology to achieve increased frequency tuning resolution. The primary N-divider was implemented utilising current mode logic (CML) and the fractional accumulator utilising conventional CMOS. Both a conventional CMOS phase frequency detector (PFD) and a CML PFD were implemented for benchmarking purposes. A custom-built 4.4 GHz synthesizer circuit employing the IC was used to validate the research. In the 4.4 GHz synthesizer circuit, the prototype IC achieved a measured in-band phase noise plateau of L( f ) = -113 dBc/Hz at a 100 kHz frequency offset, which equates to a figure of merit (FOM) of -225 dBc/Hz. The FOM compares well with existing, but expensive, SiGe and GaAs HBT processes. Total IC power dissipation was 710 mW, which is considerably less than commercially available GaAs designs. The complete synthesizer IC was implemented in Austriamicrosystems‟ (AMS) 0.35 μm CMOS process and occupies an area of 3.15 x 2.18 mm2. Electrical, Electronic and Computer Engineering unrestricted 2013-09-07T12:36:47Z 2010-09-17 2013-09-07T12:36:47Z 2010-09-02 2010-09-17 2010-09-13 Dissertation Veale, GIP 2010, Low phase noise 2 GHz fractional-N CMOS synthesizer IC, MEng dissertation, University of Pretoria, Pretoria, viewed yymmdd < http://hdl.handle.net/2263/27921 > C10/542/gm http://hdl.handle.net/2263/27921 http://upetd.up.ac.za/thesis/available/etd-09132010-162013/ © 2010, University of Pretoria. All rights reserved. The copyright in this work vests in the University of Pretoria. No part of this work may be reproduced or transmitted in any form or by any means, without the prior written permission of the University of Pretoria. application/pdf University of Pretoria |
| spellingShingle | Cml-to-cmos converter Cml flicker noise Fractional-n Cmos pfd Cml pfd Cml 4-bit counter Cml Cml 2/3-prescaler Ssb phase noise Pulse-swallow counter Low division Programmable modulus accumulator High voltage charge-pump In-band phase noise UCTD Low phase noise 2 GHz Fractional-N CMOS synthesizer IC |
| title | Low phase noise 2 GHz Fractional-N CMOS synthesizer IC |
| title_full | Low phase noise 2 GHz Fractional-N CMOS synthesizer IC |
| title_fullStr | Low phase noise 2 GHz Fractional-N CMOS synthesizer IC |
| title_full_unstemmed | Low phase noise 2 GHz Fractional-N CMOS synthesizer IC |
| title_short | Low phase noise 2 GHz Fractional-N CMOS synthesizer IC |
| title_sort | low phase noise 2 ghz fractional n cmos synthesizer ic |
| topic | Cml-to-cmos converter Cml flicker noise Fractional-n Cmos pfd Cml pfd Cml 4-bit counter Cml Cml 2/3-prescaler Ssb phase noise Pulse-swallow counter Low division Programmable modulus accumulator High voltage charge-pump In-band phase noise UCTD |
| url | http://hdl.handle.net/2263/27921 http://upetd.up.ac.za/thesis/available/etd-09132010-162013/ |