Full Text Available
Note: Clicking the button above will open the full text document at the original institutional repository in a new window.
Hardware description language modelling and synthesis of superconducting digital circuits
Thesis (PhD)--Stellenbosch University, 2017.
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Language: | en_ZA |
| Published: |
Stellenbosch : Stellenbosch University
2017
|
| Subjects: | |
| Tags: |
No Tags, Be the first to tag this record!
|
| _version_ | 1867614109672931328 |
|---|---|
| access_status_str | Open Access |
| author | Muchuka, Nicasio Maguu |
| author2 | Fourie, Coenrad |
| author_browse | Fourie, Coenrad Muchuka, Nicasio Maguu |
| author_facet | Fourie, Coenrad Muchuka, Nicasio Maguu |
| author_sort | Muchuka, Nicasio Maguu |
| collection | Thesis |
| dc_rights_str_mv | Stellenbosch University |
| description | Thesis (PhD)--Stellenbosch University, 2017. |
| format | Thesis |
| id | oai:scholar.sun.ac.za:10019.1/101041 |
| institution | Stellenbosch University (South Africa) |
| language | en_ZA |
| last_indexed | 2026-06-10T12:46:49.061Z |
| license_str | Other — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from SUNScholar — Stellenbosch University Repository |
| publishDate | 2017 |
| publishDateRange | 2017 |
| publishDateSort | 2017 |
| publisher | Stellenbosch : Stellenbosch University |
| publisherStr | Stellenbosch : Stellenbosch University |
| record_format | dspace |
| source_str | SUNScholar — Stellenbosch University Repository |
| spelling | oai:scholar.sun.ac.za:10019.1/101041 Hardware description language modelling and synthesis of superconducting digital circuits Muchuka, Nicasio Maguu Fourie, Coenrad Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering. UCTD Computer hardware description languages Electric lines -- Superconducting -- Synthesis Electric circuits Thesis (PhD)--Stellenbosch University, 2017. ENGLISH ABSTRACT: The energy demands and computational speed in high performance computers threatens the smooth transition from petascale to exascale systems. Miniaturization has been the art used in CMOS (complementary metal oxide semiconductor) for decades, to handle these energy and speed issues, however the technology is facing physical constraints. Superconducting circuit technology is a suitable candidate for beyond CMOS technologies, but faces challenges on its design tools and design automation. In this study, methods to model single flux quantum (SFQ) based circuit using hardware description languages (HDL) are implemented and thereafter a synthesis method for Rapid SFQ circuits is carried out. This enhances the ability to design at the logic and behavior level. To begin with, a survey is carried out to identify the available free software tools and a choice is made on a suitable set of tools for use in every stage of the superconducting electronics (SCE) design process. Secondly, each of the cells in rapid single flux quantum (RSFQ) and adiabatic quantum flux parametron (AQFP) cell libraries is simulated at circuit level to extract the circuit behavior. For the RSFQ cells, timing parameters are extracted whereby the propagation delay is expressed as a mathematical function dependent on bias voltage. Thirdly, to build HDL models, a proposed method is used for the AQFP logic circuits whereas, for the RSFQ circuits the existing methods are modified to handle cell delay in a mathematical expression. The resulting HDL models constitute the corresponding AQFP and RSFQ HDL cell libraries. Finally, a proposed synthesis method utilizing the RSFQ cell library is successfully implemented and tested using adders of different data widths (one bit to 64 bits). From the proposed toolchain, it is evident that superconducting circuits can be modelled and designed using free software tools. In addition, the mathematical function used in delay representation, allows the circuit to be simulated at logic level for any value of bias voltage within the circuit’s bias margin. Moreover, the synthesis method implemented can allow logic circuit designers with little or no SCE knowledge to design SCE logic circuits. AFRIKAANSE OPSOMMING: Die energie verbruik en verwerkingspoed van hoë-spoed rekenaars bedreig die veranderings gemak waarmee sisteme vanaf peta- na exa-skaal opgeskaal kan word. Die verkleinings tegnieke wat tot dus ver deur die Complimentary Metal Oxide Semiconductor (CMOS) gemeenskap gebruik word om die tegnologie af te skaal het die fisiese perke van die tegnologie bereik. Supergeleidende geïntegreerde stroombaan tegnologie is ‘n gepaste kandidaat vir die vervang van CMOS-tegnologieë, maar het nog talle probleme as dit kom by die ontwerp sagteware en outomatisering. In die studie word metodes ondersoek en beskryf om Single Flux Quantum (SFQ) stroombane te modelleer deur middel van Hardware Description Language (HDL); waarna ‘n sintese metode gebruik word om ‘n Rapid Single Flux Quantum (RSFQ) stroombaan te sinteseer. Dié verhoog die gehalte van ontwerp wat op ‘n logika en gedragsvlak gedoen kan word. ‘n Steekproef word eers gedoen om die relevante sagteware pakkette te identifiseer wat vrylik beskikbaar is, waarna ‘n besluit geneem word oor die stel sagteware wat gepas is vir elke stadium van die ontwerp proses. Tweedens word elke logiese sel in die RSFQ en Adiabatic Quantum Flux Parametron (AQFP) sel-biblioteek gesimuleer op stroombaan vlak op die stroombaan gedrag te bepaal. Vir die RSFQ selle word die tydsverloop parameters bepaal waarmee die voortplantings vertraging beskryf kan word as ‘n funksie van die voorspanning. Verder, om HDL modelle te bou, word ‘n metode voorgestel en gebruik vir AQFP stroombane. Vir RSFQ stroombane word klaar bestaande metodes aangepas om wiskundig die selvertraging in ag te neem. Die resulterende HDL modelle bevat dan beide die AQFP en RSFQ HDL selbiblioteke. Laastens word ‘n voorgestelde sintese metode, gerig op RSFQ selle, suksesvol geïmplementeer waarna dit getoets word met sommeerders van verskillende data wydtes (1 tot 64 bis). Die voorgestelde sagteware pakket beloof dus om dit moontlik te maak vir ontwerpers om supergeleidende geïntegreerde stroombane te kan ontwerp en modelleer met slegs vrylik beskikbare sagteware. Daarbenewens laat die wiskundige vergelykings wat gebruik word vir die verteenwoordiging van logikavertraaging toe dat ‘n stoombaan gesimuleer kan word op logika vlak vir enige voorspanning solank dit binne die perke van die stroombaan bly. Verder kan die sintese metode wat geïmplementeer word, logika ontwerpers toelaat om stroombane te ontwerp, al het hul geen kennis van supergeleidende stroombaan ontwerp nie. Doctoral 2017-02-14T10:26:55Z 2017-03-29T12:01:11Z 2017-02-14T10:26:55Z 2017-03-29T12:01:11Z 2017-03 Thesis http://hdl.handle.net/10019.1/101041 en_ZA Stellenbosch University 96 pages : illustrations application/pdf Stellenbosch : Stellenbosch University |
| spellingShingle | UCTD Computer hardware description languages Electric lines -- Superconducting -- Synthesis Electric circuits Muchuka, Nicasio Maguu Hardware description language modelling and synthesis of superconducting digital circuits |
| title | Hardware description language modelling and synthesis of superconducting digital circuits |
| title_full | Hardware description language modelling and synthesis of superconducting digital circuits |
| title_fullStr | Hardware description language modelling and synthesis of superconducting digital circuits |
| title_full_unstemmed | Hardware description language modelling and synthesis of superconducting digital circuits |
| title_short | Hardware description language modelling and synthesis of superconducting digital circuits |
| title_sort | hardware description language modelling and synthesis of superconducting digital circuits |
| topic | UCTD Computer hardware description languages Electric lines -- Superconducting -- Synthesis Electric circuits |
| url | http://hdl.handle.net/10019.1/101041 |
| work_keys_str_mv | AT muchukanicasiomaguu hardwaredescriptionlanguagemodellingandsynthesisofsuperconductingdigitalcircuits |