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Synthesis, placement and routing tools for RSFQ digital integrated circuit design
Thesis (MEng)--Stellenbosch University, 2023.
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| Format: | Thesis |
| Language: | en_ZA en_ZA |
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Stellenbosch : Stellenbosch University
2023
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| _version_ | 1867613976088543232 |
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| access_status_str | Open Access |
| author | Verburg, Edrich |
| author2 | Fourie, Coenrad |
| author_browse | Fourie, Coenrad Verburg, Edrich |
| author_facet | Fourie, Coenrad Verburg, Edrich |
| author_sort | Verburg, Edrich |
| collection | Thesis |
| dc_rights_str_mv | Stellenbosch University |
| description | Thesis (MEng)--Stellenbosch University, 2023. |
| format | Thesis |
| id | oai:scholar.sun.ac.za:10019.1/127025 |
| institution | Stellenbosch University (South Africa) |
| language | en_ZA en_ZA |
| last_indexed | 2026-06-10T12:44:41.678Z |
| license_str | Other — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from SUNScholar — Stellenbosch University Repository |
| publishDate | 2023 |
| publishDateRange | 2023 |
| publishDateSort | 2023 |
| publisher | Stellenbosch : Stellenbosch University |
| publisherStr | Stellenbosch : Stellenbosch University |
| record_format | dspace |
| source_str | SUNScholar — Stellenbosch University Repository |
| spelling | oai:scholar.sun.ac.za:10019.1/127025 Synthesis, placement and routing tools for RSFQ digital integrated circuit design Verburg, Edrich Fourie, Coenrad Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering. Synthesis, placement and routing tools; RSFQ; digital integrated circuit design Software synthesizers Combinational circuits Back propagation (Artificial intelligence) Verilog (Computer hardware description language) Thesis (MEng)--Stellenbosch University, 2023. ENGLISH ABSTRACT: ViPeR is a Stellenbosch developed software tool chain for high-level synthesis, placement, routing and verification of superconducting combinational logic circuits - specifically within the RSFQ logic family and using the SFQ5ee process for layout. The aim of the work presented in this thesis is to analyze the internals of ViPeR in an attempt to imporove it so that it is capable of more effective synthesis and verification on a larger scale. Automated synthesis, placement and routing methods and tools are discussed. The ViPeR tool chain is discussed along with its capabilities and limitations. Solutions to ViPeR’s limitations are discussed. The implementation details and results of these solutions are discussed. The full functionality of the improved ViPeR tool chain is showcased with the synthesis and verification of combinational circuits of various sizes. The most important result of this functionality showcase is the complete synthesis and verification of a 32-bit Ripple Carry Adder that operates without timing violations at 6.7 GHz. These results are discussed and recommendations are presented. It is concluded that ViPeR is a fast, complete and accessible tool chain for the synthesis and verification of medium to large scale combinational RSFQ circuits. AFRIKAANS OPSOMMING: ViPeR is ’n Stellenbosch-ontwikkelde sagteware-gereedskapsketting vir ho¨evlak sintese, plasing, roetering en verifikasie van supergeleidende kombinasionele stroombane - spesifiek binne die RSFQ-logikafamilie en wat die SFQ5ee-proses gebruik vir uitleg. Die doel van die werk wat in hierdie tesis aangebied word, is om die werking van ViPeR te analiseer in ’n poging om dit te verbeter sodat dit in staat is tot meer effektiewe sintese en verifikasie op ’n groter skaal. Outomatiese sintese, plasing en roeteringsmetodes en sagteware word bespreek. Die ViPeR-gereedskapsketting word saam met sy vermo¨ens en beperkings bespreek. Oplossings vir ViPeR se beperkings word bespreek. Die implementeringsbesonderhede en resultate van hierdie oplossings word bespreek. Die volle funksionaliteit van die verbeterde ViPeR-gereedskapsketting word vertoon met die sintese en verifikasie van kombinasionele stroombane van verskillende groottes. Die belangrikste resultaat van hierdie vertoonde funksionaliteit is die volledige sintese en verifikasie van ’n 32-bis “Ripple Carry Adder” wat werk sonder enige tydsberekening oortredings by 6.7 GHz. Hierdie resultate word bespreek en aanbevelings word aangebied. Daar word tot die gevolgtrekking gekom dat ViPeR ’n vinnige, volledige en toeganklike gereedskapsketting is vir die sintese en verifikasie van medium- tot grootskaalse RSFQ kombinasionele stroombane. Masters 2023-03-03T09:19:49Z 2023-05-18T07:00:40Z 2023-03-03T09:19:49Z 2023-05-18T07:00:40Z 2023-03-30 Thesis http://hdl.handle.net/10019.1/127025 en_ZA en_ZA Stellenbosch University xii, 85 pages : illustrations application/pdf Stellenbosch : Stellenbosch University |
| spellingShingle | Synthesis, placement and routing tools; RSFQ; digital integrated circuit design Software synthesizers Combinational circuits Back propagation (Artificial intelligence) Verilog (Computer hardware description language) Verburg, Edrich Synthesis, placement and routing tools for RSFQ digital integrated circuit design |
| title | Synthesis, placement and routing tools for RSFQ digital integrated circuit design |
| title_full | Synthesis, placement and routing tools for RSFQ digital integrated circuit design |
| title_fullStr | Synthesis, placement and routing tools for RSFQ digital integrated circuit design |
| title_full_unstemmed | Synthesis, placement and routing tools for RSFQ digital integrated circuit design |
| title_short | Synthesis, placement and routing tools for RSFQ digital integrated circuit design |
| title_sort | synthesis placement and routing tools for rsfq digital integrated circuit design |
| topic | Synthesis, placement and routing tools; RSFQ; digital integrated circuit design Software synthesizers Combinational circuits Back propagation (Artificial intelligence) Verilog (Computer hardware description language) |
| url | http://hdl.handle.net/10019.1/127025 |
| work_keys_str_mv | AT verburgedrich synthesisplacementandroutingtoolsforrsfqdigitalintegratedcircuitdesign |