Full Text Available

Note: Clicking the button above will open the full text document at the original institutional repository in a new window.

First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES

Saved in:
Bibliographic Details
Published in:Journal of Cryptographic Engineering
Format: Online Article RSS Article
Published: 2026
Subjects:
Tags: Add Tag
No Tags, Be the first to tag this record!