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Model Checking Vector Addition Systems with one zero-test

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Bibliographic Details
Published in:Logical Methods in Computer Science
Format: Online Article RSS Article
Published: 2012
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container_title Logical Methods in Computer Science
description
discipline_display Engineering & Technology
discipline_facet Engineering & Technology
format Online Article
RSS Article
genre Journal Article
id rss_article:6415
institution FRELIP
journal_source_facet Logical Methods in Computer Science
publishDate 2012
publishDateSort 2012
record_format rss_article
spellingShingle Model Checking Vector Addition Systems with one zero-test
Computer Science & Information Science
Computer Science & IT
Engineering & Technology
sub_discipline_display Computer Science & IT
sub_discipline_facet Computer Science & IT
subject_display Computer Science & Information Science
Computer Science & IT
Engineering & Technology
Computer Science & Information Science
Computer Science & IT
Engineering & Technology
subject_facet Computer Science & Information Science
Computer Science & IT
Engineering & Technology
title Model Checking Vector Addition Systems with one zero-test
title_auth Model Checking Vector Addition Systems with one zero-test
title_full Model Checking Vector Addition Systems with one zero-test
title_fullStr Model Checking Vector Addition Systems with one zero-test
title_full_unstemmed Model Checking Vector Addition Systems with one zero-test
title_short Model Checking Vector Addition Systems with one zero-test
title_sort model checking vector addition systems with one zero-test
topic Computer Science & Information Science
Computer Science & IT
Engineering & Technology
url https://doi.org/10.2168/LMCS-8(2:11)2012