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Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory

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Bibliographic Details
Published in:IEEE Journal of the Electron Devices Society
Format: Online Article RSS Article
Published: 2026
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container_title IEEE Journal of the Electron Devices Society
description
discipline_display Electronics
discipline_facet Electronics
format Online Article
RSS Article
genre Journal Article
id rss_article:74180
institution FRELIP
journal_source_facet IEEE Journal of the Electron Devices Society
publishDate 2026
publishDateSort 2026
record_format rss_article
spellingShingle Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory
Electronics
General
Electronics
sub_discipline_display General
sub_discipline_facet General
subject_display Electronics
General
Electronics
Electronics
General
Electronics
subject_facet Electronics
General
Electronics
title Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory
title_auth Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory
title_full Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory
title_fullStr Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory
title_full_unstemmed Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory
title_short Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory
title_sort low-power stack-level programming enabled by optimized dummy word line voltage in 3-d nand flash memory
topic Electronics
General
Electronics
url http://ieeexplore.ieee.org/document/11367431