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On the production testing of analog and digital circuits
This thesis focuses on the production testing of Analog and Digital circuits. First, it addresses the issue of finding a high coverage minimum test set for the second generation current conveyor as this was not tackled before. The circuit under test is used in active capacitance multipliers, V-I sca...
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| Format: | Thesis |
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AUC Knowledge Fountain
2016
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| _version_ | 1867613409186414592 |
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| access_status_str | Open Access |
| author | A.S. Emara, Ahmed Shukry |
| author_browse | A.S. Emara, Ahmed Shukry |
| author_facet | A.S. Emara, Ahmed Shukry |
| author_sort | A.S. Emara, Ahmed Shukry |
| collection | Thesis |
| dc_rights_str_mv | The author retains all rights with regard to copyright. The author certifies that written permission from the owner(s) of third-party copyrighted matter included in the thesis, dissertation, paper, or record of study has been obtained. The author further certifies that IRB approval has been obtained for this thesis, or that IRB approval is not necessary for this thesis. Insofar as this thesis, dissertation, paper, or record of study is an educational record as defined in the Family Educational Rights and Privacy Act (FERPA) (20 USC 1232g), the author has granted consent to disclosure of it to anyone who requests a copy. |
| description | This thesis focuses on the production testing of Analog and Digital circuits. First, it addresses the issue of finding a high coverage minimum test set for the second generation current conveyor as this was not tackled before. The circuit under test is used in active capacitance multipliers, V-I scalar circuits, Biquadratic filters and many other applications. This circuit is often used to implement voltage followers, current followers and voltage to current converters. Five faults are assumed per transistor. It is shown that, to obtain 100% fault coverage, the CCII has to be operated in voltage to current converter mode. Only two test values are required to obtain this fault coverage. Additionally, the thesis focuses on the production testing of Memristor Ratioed Logic (MRL) gates because this was not studied before. MRL is a family that uses memristors along with CMOS inverters to design logic gates. Two-input NAND and NOR gates are investigated using the stuck at fault model for the memristors and the five-fault model for the transistors. It is shown that in order to obtain full coverage for the MRL NAND and NOR gates, two solutions are proposed. The first is the usage of scaled input voltages to prevent the output from falling in the undefined region. The second proposed solution is changing the switching threshold VM of the CMOS inverter. In addition, it is shown that test speed and order should be taken into consideration. It is proven that three ordered test vectors are needed for full coverage in MRL NAND and NOR gates, which is different from the 100% coverage test set in the conventional NAND and NOR CMOS designs. |
| format | Thesis |
| id | oai:fount.aucegypt.edu:etds-1250 |
| institution | American University in Cairo (Egypt) |
| last_indexed | 2026-06-10T12:35:41.195Z |
| license_str | Other — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from AUC Knowledge Fountain — bepress |
| publishDate | 2016 |
| publishDateRange | 2016 |
| publishDateSort | 2016 |
| publisher | AUC Knowledge Fountain |
| publisherStr | AUC Knowledge Fountain |
| record_format | dspace |
| source_str | AUC Knowledge Fountain — bepress |
| spelling | oai:fount.aucegypt.edu:etds-1250 On the production testing of analog and digital circuits A.S. Emara, Ahmed Shukry This thesis focuses on the production testing of Analog and Digital circuits. First, it addresses the issue of finding a high coverage minimum test set for the second generation current conveyor as this was not tackled before. The circuit under test is used in active capacitance multipliers, V-I scalar circuits, Biquadratic filters and many other applications. This circuit is often used to implement voltage followers, current followers and voltage to current converters. Five faults are assumed per transistor. It is shown that, to obtain 100% fault coverage, the CCII has to be operated in voltage to current converter mode. Only two test values are required to obtain this fault coverage. Additionally, the thesis focuses on the production testing of Memristor Ratioed Logic (MRL) gates because this was not studied before. MRL is a family that uses memristors along with CMOS inverters to design logic gates. Two-input NAND and NOR gates are investigated using the stuck at fault model for the memristors and the five-fault model for the transistors. It is shown that in order to obtain full coverage for the MRL NAND and NOR gates, two solutions are proposed. The first is the usage of scaled input voltages to prevent the output from falling in the undefined region. The second proposed solution is changing the switching threshold VM of the CMOS inverter. In addition, it is shown that test speed and order should be taken into consideration. It is proven that three ordered test vectors are needed for full coverage in MRL NAND and NOR gates, which is different from the 100% coverage test set in the conventional NAND and NOR CMOS designs. 2016-06-01T07:00:00Z thesis application/pdf https://fount.aucegypt.edu/etds/251 https://fount.aucegypt.edu/context/etds/article/1250/viewcontent/AhmedEmaraTHESIS.revised.pdf The author retains all rights with regard to copyright. The author certifies that written permission from the owner(s) of third-party copyrighted matter included in the thesis, dissertation, paper, or record of study has been obtained. The author further certifies that IRB approval has been obtained for this thesis, or that IRB approval is not necessary for this thesis. Insofar as this thesis, dissertation, paper, or record of study is an educational record as defined in the Family Educational Rights and Privacy Act (FERPA) (20 USC 1232g), the author has granted consent to disclosure of it to anyone who requests a copy. Theses and Dissertations AUC Knowledge Fountain Production Testing Fault Models |
| spellingShingle | Production Testing Fault Models A.S. Emara, Ahmed Shukry On the production testing of analog and digital circuits |
| title | On the production testing of analog and digital circuits |
| title_full | On the production testing of analog and digital circuits |
| title_fullStr | On the production testing of analog and digital circuits |
| title_full_unstemmed | On the production testing of analog and digital circuits |
| title_short | On the production testing of analog and digital circuits |
| title_sort | on the production testing of analog and digital circuits |
| topic | Production Testing Fault Models |
| url | https://fount.aucegypt.edu/etds/251 https://fount.aucegypt.edu/context/etds/article/1250/viewcontent/AhmedEmaraTHESIS.revised.pdf |
| work_keys_str_mv | AT asemaraahmedshukry ontheproductiontestingofanaloganddigitalcircuits |