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Fault Modeling and Test Vector Generation for ASIC Devices Exposed to Space Single Event Environment
This work aims at providing a concise automated flow to predict the effect of Single Event Transients (SETs) on ASIC chips by developing a method to characterize the circuit susceptibility to SET pulses propagation and then generation of the required input vectors that sensitize the victim paths. A...
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AUC Knowledge Fountain
2021
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