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Fault Modeling and Test Vector Generation for ASIC Devices Exposed to Space Single Event Environment
This work aims at providing a concise automated flow to predict the effect of Single Event Transients (SETs) on ASIC chips by developing a method to characterize the circuit susceptibility to SET pulses propagation and then generation of the required input vectors that sensitize the victim paths. A...
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| Format: | Thesis |
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AUC Knowledge Fountain
2021
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| _version_ | 1867613419300978688 |
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| access_status_str | Open Access |
| author | Mohamed, Ahmed |
| author_browse | Mohamed, Ahmed |
| author_facet | Mohamed, Ahmed |
| author_sort | Mohamed, Ahmed |
| collection | Thesis |
| description | This work aims at providing a concise automated flow to predict the effect of Single Event Transients (SETs) on ASIC chips by developing a method to characterize the circuit susceptibility to SET pulses propagation and then generation of the required input vectors that sensitize the victim paths. A new enhanced method for SET electrical propagation modeling is proposed and compared to a previously published analytical model. The method was applied on different standard cells libraries built over XFAB Xh018 technology and verified for accuracy against simulations. The new method showed enhancement in accuracy compared with previous work in literature. Industrial ATPG tool for SET test vectors generation was used with some modifications to its native flow to fit the different nature of SETs. The proposed steps were tested using ISCAS ’85 benchmarks synthesized with the XFAB standard cells. |
| format | Thesis |
| id | oai:fount.aucegypt.edu:etds-2669 |
| institution | American University in Cairo (Egypt) |
| last_indexed | 2026-06-10T12:35:50.652Z |
| license_str | Not specified — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from AUC Knowledge Fountain — bepress |
| publishDate | 2021 |
| publishDateRange | 2021 |
| publishDateSort | 2021 |
| publisher | AUC Knowledge Fountain |
| publisherStr | AUC Knowledge Fountain |
| record_format | dspace |
| source_str | AUC Knowledge Fountain — bepress |
| spelling | oai:fount.aucegypt.edu:etds-2669 Fault Modeling and Test Vector Generation for ASIC Devices Exposed to Space Single Event Environment Mohamed, Ahmed This work aims at providing a concise automated flow to predict the effect of Single Event Transients (SETs) on ASIC chips by developing a method to characterize the circuit susceptibility to SET pulses propagation and then generation of the required input vectors that sensitize the victim paths. A new enhanced method for SET electrical propagation modeling is proposed and compared to a previously published analytical model. The method was applied on different standard cells libraries built over XFAB Xh018 technology and verified for accuracy against simulations. The new method showed enhancement in accuracy compared with previous work in literature. Industrial ATPG tool for SET test vectors generation was used with some modifications to its native flow to fit the different nature of SETs. The proposed steps were tested using ISCAS ’85 benchmarks synthesized with the XFAB standard cells. 2021-05-25T07:00:00Z thesis application/pdf https://fount.aucegypt.edu/etds/1645 https://fount.aucegypt.edu/context/etds/article/2669/viewcontent/ahmed_ibrahim_mohamed_thesis.pdf https://fount.aucegypt.edu/context/etds/article/2669/filename/0/type/additional/viewcontent/ahmed_ibrahim_mohamed_signature.pdf https://fount.aucegypt.edu/context/etds/article/2669/filename/1/type/additional/viewcontent/ahmed_ibrahim_mohamed_irb.pdf https://fount.aucegypt.edu/context/etds/article/2669/filename/2/type/additional/viewcontent/ahmed_ibrahim_mohamed_turnitin.pdf Theses and Dissertations AUC Knowledge Fountain ASIC SET ATPG Fault Modelling Test Vectors Standard Cells Electrical and Electronics Electronic Devices and Semiconductor Manufacturing VLSI and Circuits, Embedded and Hardware Systems |
| spellingShingle | ASIC SET ATPG Fault Modelling Test Vectors Standard Cells Electrical and Electronics Electronic Devices and Semiconductor Manufacturing VLSI and Circuits, Embedded and Hardware Systems Mohamed, Ahmed Fault Modeling and Test Vector Generation for ASIC Devices Exposed to Space Single Event Environment |
| title | Fault Modeling and Test Vector Generation for ASIC Devices Exposed to Space Single Event Environment |
| title_full | Fault Modeling and Test Vector Generation for ASIC Devices Exposed to Space Single Event Environment |
| title_fullStr | Fault Modeling and Test Vector Generation for ASIC Devices Exposed to Space Single Event Environment |
| title_full_unstemmed | Fault Modeling and Test Vector Generation for ASIC Devices Exposed to Space Single Event Environment |
| title_short | Fault Modeling and Test Vector Generation for ASIC Devices Exposed to Space Single Event Environment |
| title_sort | fault modeling and test vector generation for asic devices exposed to space single event environment |
| topic | ASIC SET ATPG Fault Modelling Test Vectors Standard Cells Electrical and Electronics Electronic Devices and Semiconductor Manufacturing VLSI and Circuits, Embedded and Hardware Systems |
| url | https://fount.aucegypt.edu/etds/1645 https://fount.aucegypt.edu/context/etds/article/2669/viewcontent/ahmed_ibrahim_mohamed_thesis.pdf https://fount.aucegypt.edu/context/etds/article/2669/filename/0/type/additional/viewcontent/ahmed_ibrahim_mohamed_signature.pdf https://fount.aucegypt.edu/context/etds/article/2669/filename/1/type/additional/viewcontent/ahmed_ibrahim_mohamed_irb.pdf https://fount.aucegypt.edu/context/etds/article/2669/filename/2/type/additional/viewcontent/ahmed_ibrahim_mohamed_turnitin.pdf |
| work_keys_str_mv | AT mohamedahmed faultmodelingandtestvectorgenerationforasicdevicesexposedtospacesingleeventenvironment |