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Synthesizable delay line architectures for digitally controlled voltage regulators
Voltage regulators used in the integrated circuit (IC) industry require precise voltage regulation. In digitally controlled switching converters, this precise voltage regulation is achieved by high resolution digital pulse width modulators (DPWM). Digital delay lines can be used to generate the puls...
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| Format: | Thesis |
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AUC Knowledge Fountain
2013
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| _version_ | 1867613416570486784 |
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| access_status_str | Open Access |
| author | Haridy, Omar Fathy |
| author_browse | Haridy, Omar Fathy |
| author_facet | Haridy, Omar Fathy |
| author_sort | Haridy, Omar Fathy |
| collection | Thesis |
| dc_rights_str_mv | The author retains all rights with regard to copyright. The author certifies that written permission from the owner(s) of third-party copyrighted matter included in the thesis, dissertation, paper, or record of study has been obtained. The author further certifies that IRB approval has been obtained for this thesis, or that IRB approval is not necessary for this thesis. Insofar as this thesis, dissertation, paper, or record of study is an educational record as defined in the Family Educational Rights and Privacy Act (FERPA) (20 USC 1232g), the author has granted consent to disclosure of it to anyone who requests a copy. |
| description | Voltage regulators used in the integrated circuit (IC) industry require precise voltage regulation. In digitally controlled switching converters, this precise voltage regulation is achieved by high resolution digital pulse width modulators (DPWM). Digital delay lines can be used to generate the pulse width modulation (PWM) signal. Conventional delay lines are designed in a full custom design methodology which is extremely slow and expensive compared to register-transfer level (RTL) based designs; also RTL based designs are technology independent so the same design can be used with new technologies. The purpose of this work is to introduce a new architecture for the fully synthesizable digital delay line used in digitally controlled voltage regulators. A comparison between the proposed scheme and the conventional delay line is done post synthesis on the key delay line specifications like linearity, area, complexity, and compensation for process, voltage, and temperature (PVT) variations for multiple clock frequencies. Both schemes are designed using a hardware description language (HDL) and synthesized using Intel 32nm technology. The comparison showed that the proposed architecture has better linearity, area, and also it has a fast calibration time with respect to conventional delay lines. The delay lines are designed in parameterized way in order to make the design suitable for multiple frequencies. |
| format | Thesis |
| id | oai:fount.aucegypt.edu:etds-2238 |
| institution | American University in Cairo (Egypt) |
| last_indexed | 2026-06-10T12:35:47.730Z |
| license_str | Other — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from AUC Knowledge Fountain — bepress |
| publishDate | 2013 |
| publishDateRange | 2013 |
| publishDateSort | 2013 |
| publisher | AUC Knowledge Fountain |
| publisherStr | AUC Knowledge Fountain |
| record_format | dspace |
| source_str | AUC Knowledge Fountain — bepress |
| spelling | oai:fount.aucegypt.edu:etds-2238 Synthesizable delay line architectures for digitally controlled voltage regulators Haridy, Omar Fathy Voltage regulators used in the integrated circuit (IC) industry require precise voltage regulation. In digitally controlled switching converters, this precise voltage regulation is achieved by high resolution digital pulse width modulators (DPWM). Digital delay lines can be used to generate the pulse width modulation (PWM) signal. Conventional delay lines are designed in a full custom design methodology which is extremely slow and expensive compared to register-transfer level (RTL) based designs; also RTL based designs are technology independent so the same design can be used with new technologies. The purpose of this work is to introduce a new architecture for the fully synthesizable digital delay line used in digitally controlled voltage regulators. A comparison between the proposed scheme and the conventional delay line is done post synthesis on the key delay line specifications like linearity, area, complexity, and compensation for process, voltage, and temperature (PVT) variations for multiple clock frequencies. Both schemes are designed using a hardware description language (HDL) and synthesized using Intel 32nm technology. The comparison showed that the proposed architecture has better linearity, area, and also it has a fast calibration time with respect to conventional delay lines. The delay lines are designed in parameterized way in order to make the design suitable for multiple frequencies. 2013-02-01T08:00:00Z thesis application/pdf https://fount.aucegypt.edu/etds/1239 https://fount.aucegypt.edu/context/etds/article/2238/viewcontent/Omar_Haridy_Thesis.pdf The author retains all rights with regard to copyright. The author certifies that written permission from the owner(s) of third-party copyrighted matter included in the thesis, dissertation, paper, or record of study has been obtained. The author further certifies that IRB approval has been obtained for this thesis, or that IRB approval is not necessary for this thesis. Insofar as this thesis, dissertation, paper, or record of study is an educational record as defined in the Family Educational Rights and Privacy Act (FERPA) (20 USC 1232g), the author has granted consent to disclosure of it to anyone who requests a copy. Theses and Dissertations AUC Knowledge Fountain Digital control Delay Locked Loops (DLL) |
| spellingShingle | Digital control Delay Locked Loops (DLL) Haridy, Omar Fathy Synthesizable delay line architectures for digitally controlled voltage regulators |
| title | Synthesizable delay line architectures for digitally controlled voltage regulators |
| title_full | Synthesizable delay line architectures for digitally controlled voltage regulators |
| title_fullStr | Synthesizable delay line architectures for digitally controlled voltage regulators |
| title_full_unstemmed | Synthesizable delay line architectures for digitally controlled voltage regulators |
| title_short | Synthesizable delay line architectures for digitally controlled voltage regulators |
| title_sort | synthesizable delay line architectures for digitally controlled voltage regulators |
| topic | Digital control Delay Locked Loops (DLL) |
| url | https://fount.aucegypt.edu/etds/1239 https://fount.aucegypt.edu/context/etds/article/2238/viewcontent/Omar_Haridy_Thesis.pdf |
| work_keys_str_mv | AT haridyomarfathy synthesizabledelaylinearchitecturesfordigitallycontrolledvoltageregulators |