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First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES
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| Published in: | Journal of Cryptographic Engineering |
|---|---|
| Format: | Online Article RSS Article |
| Published: |
2026
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| Subjects: | |
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| _version_ | 1867301674255646722 |
|---|---|
| collection | WordPress RSS FRELIP Feed Integration |
| container_title | Journal of Cryptographic Engineering |
| description | |
| discipline_display | Computer and Cyber Security |
| discipline_facet | Computer and Cyber Security |
| format | Online Article RSS Article |
| genre | Journal Article |
| id | rss_article:77525 |
| institution | FRELIP |
| journal_source_facet | Journal of Cryptographic Engineering |
| publishDate | 2026 |
| publishDateSort | 2026 |
| record_format | rss_article |
| spellingShingle | First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES Computer and Cyber Security General Computer and Cyber Security |
| sub_discipline_display | General |
| sub_discipline_facet | General |
| subject_display | Computer and Cyber Security General Computer and Cyber Security Computer and Cyber Security General Computer and Cyber Security |
| subject_facet | Computer and Cyber Security General Computer and Cyber Security |
| title | First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES |
| title_auth | First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES |
| title_full | First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES |
| title_fullStr | First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES |
| title_full_unstemmed | First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES |
| title_short | First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES |
| title_sort | first fully pipelined high throughput fpga implementation and gpu optimization of wider variant of aes |
| topic | Computer and Cyber Security General Computer and Cyber Security |
| url | https://link.springer.com/article/10.1007/s13389-025-00388-2 |