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Layout regularity metric as a fast indicator of process variations
Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are...
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AUC Knowledge Fountain
2014
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| _version_ | 1867613416585166848 |
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| access_status_str | Open Access |
| author | Swillam, Esraa AbdelAzim AbdelHamid |
| author_browse | Swillam, Esraa AbdelAzim AbdelHamid |
| author_facet | Swillam, Esraa AbdelAzim AbdelHamid |
| author_sort | Swillam, Esraa AbdelAzim AbdelHamid |
| collection | Thesis |
| dc_rights_str_mv | The author retains all rights with regard to copyright. The author certifies that written permission from the owner(s) of third-party copyrighted matter included in the thesis, dissertation, paper, or record of study has been obtained. The author further certifies that IRB approval has been obtained for this thesis, or that IRB approval is not necessary for this thesis. Insofar as this thesis, dissertation, paper, or record of study is an educational record as defined in the Family Educational Rights and Privacy Act (FERPA) (20 USC 1232g), the author has granted consent to disclosure of it to anyone who requests a copy. |
| description | Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations. |
| format | Thesis |
| id | oai:fount.aucegypt.edu:etds-2242 |
| institution | American University in Cairo (Egypt) |
| last_indexed | 2026-06-10T12:35:47.730Z |
| license_str | Other — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from AUC Knowledge Fountain — bepress |
| publishDate | 2014 |
| publishDateRange | 2014 |
| publishDateSort | 2014 |
| publisher | AUC Knowledge Fountain |
| publisherStr | AUC Knowledge Fountain |
| record_format | dspace |
| source_str | AUC Knowledge Fountain — bepress |
| spelling | oai:fount.aucegypt.edu:etds-2242 Layout regularity metric as a fast indicator of process variations Swillam, Esraa AbdelAzim AbdelHamid Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations. 2014-06-01T07:00:00Z thesis application/pdf https://fount.aucegypt.edu/etds/1243 https://fount.aucegypt.edu/context/etds/article/2242/viewcontent/Esraa_swillam_corrected_thesis.pdf The author retains all rights with regard to copyright. The author certifies that written permission from the owner(s) of third-party copyrighted matter included in the thesis, dissertation, paper, or record of study has been obtained. The author further certifies that IRB approval has been obtained for this thesis, or that IRB approval is not necessary for this thesis. Insofar as this thesis, dissertation, paper, or record of study is an educational record as defined in the Family Educational Rights and Privacy Act (FERPA) (20 USC 1232g), the author has granted consent to disclosure of it to anyone who requests a copy. Theses and Dissertations AUC Knowledge Fountain VLSI design methods Lithography |
| spellingShingle | VLSI design methods Lithography Swillam, Esraa AbdelAzim AbdelHamid Layout regularity metric as a fast indicator of process variations |
| title | Layout regularity metric as a fast indicator of process variations |
| title_full | Layout regularity metric as a fast indicator of process variations |
| title_fullStr | Layout regularity metric as a fast indicator of process variations |
| title_full_unstemmed | Layout regularity metric as a fast indicator of process variations |
| title_short | Layout regularity metric as a fast indicator of process variations |
| title_sort | layout regularity metric as a fast indicator of process variations |
| topic | VLSI design methods Lithography |
| url | https://fount.aucegypt.edu/etds/1243 https://fount.aucegypt.edu/context/etds/article/2242/viewcontent/Esraa_swillam_corrected_thesis.pdf |
| work_keys_str_mv | AT swillamesraaabdelazimabdelhamid layoutregularitymetricasafastindicatorofprocessvariations |