Full Text Available
Note: Clicking the button above will open the full text document at the original institutional repository in a new window.
Identifying worst case test vectors for FPGA exposed to total ionization dose using design for testability techniques
Electronic devices often operate in harsh environments which contain a variation of radiation sources. Radiation may cause different kinds of damage to proper operation of the devices. Their sources can be found in terrestrial environments, or in extra-terrestrial environments like in space, or in m...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Published: |
AUC Knowledge Fountain
2018
|
| Subjects: | |
| Tags: |
No Tags, Be the first to tag this record!
|
| _version_ | 1867613417766912000 |
|---|---|
| access_status_str | Open Access |
| author | Abdelwahab, Mohamed Sami |
| author_browse | Abdelwahab, Mohamed Sami |
| author_facet | Abdelwahab, Mohamed Sami |
| author_sort | Abdelwahab, Mohamed Sami |
| collection | Thesis |
| dc_rights_str_mv | The author retains all rights with regard to copyright. The author certifies that written permission from the owner(s) of third-party copyrighted matter included in the thesis, dissertation, paper, or record of study has been obtained. The author further certifies that IRB approval has been obtained for this thesis, or that IRB approval is not necessary for this thesis. Insofar as this thesis, dissertation, paper, or record of study is an educational record as defined in the Family Educational Rights and Privacy Act (FERPA) (20 USC 1232g), the author has granted consent to disclosure of it to anyone who requests a copy. The author has granted the American University in Cairo or its agents a non-exclusive license to archive this thesis, dissertation, paper, or record of study, and to make it accessible, in whole or in part, in all forms of media, now or hereafter known. |
| description | Electronic devices often operate in harsh environments which contain a variation of radiation sources. Radiation may cause different kinds of damage to proper operation of the devices. Their sources can be found in terrestrial environments, or in extra-terrestrial environments like in space, or in man-made radiation sources like nuclear reactors, biomedical devices and high energy particles physics experiments equipment. Depending on the operation environment of the device, the radiation resultant effect manifests in several forms like total ionizing dose effect (TID), or single event effects (SEEs) such as single event upset (SEU), single event gate rupture (SEGR), and single event latch up (SEL). TID effect causes an increase in the delay and the leakage current of CMOS circuits which may damage the proper operation of the integrated circuit. To ensure proper operation of these devices under radiation, thorough testing must be made especially in critical applications like space and military applications. Although the standard which describes the procedure for testing electronic devices under radiation emphasizes the use of worst case test vectors (WCTVs), they are never used in radiation testing due to the difficulty of generating these vectors for circuits under test. For decades, design for testability (DFT) has been the best choice for test engineers to test digital circuits in industry. It has become a very mature technology that can be relied on. DFT is usually used with automatic test patterns generation (ATPG) software to generate test vectors to test application specific integrated circuits (ASICs), especially with sequential circuits, against faults like stuck at faults and path delay faults. Surprisingly, however, radiation testing has not yet made use of this reliable technology. In this thesis, a novel methodology is proposed to extend the usage of DFT to generate WCTVs for delay failure in Flash based field programmable gate arrays (FPGAs) exposed to total ionizing dose (TID). The methodology is validated using MicroSemi ProASIC3 FPGA and cobalt 60 facility. |
| format | Thesis |
| id | oai:fount.aucegypt.edu:etds-2348 |
| institution | American University in Cairo (Egypt) |
| last_indexed | 2026-06-10T12:35:48.888Z |
| license_str | Other — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from AUC Knowledge Fountain — bepress |
| publishDate | 2018 |
| publishDateRange | 2018 |
| publishDateSort | 2018 |
| publisher | AUC Knowledge Fountain |
| publisherStr | AUC Knowledge Fountain |
| record_format | dspace |
| source_str | AUC Knowledge Fountain — bepress |
| spelling | oai:fount.aucegypt.edu:etds-2348 Identifying worst case test vectors for FPGA exposed to total ionization dose using design for testability techniques Abdelwahab, Mohamed Sami Electronic devices often operate in harsh environments which contain a variation of radiation sources. Radiation may cause different kinds of damage to proper operation of the devices. Their sources can be found in terrestrial environments, or in extra-terrestrial environments like in space, or in man-made radiation sources like nuclear reactors, biomedical devices and high energy particles physics experiments equipment. Depending on the operation environment of the device, the radiation resultant effect manifests in several forms like total ionizing dose effect (TID), or single event effects (SEEs) such as single event upset (SEU), single event gate rupture (SEGR), and single event latch up (SEL). TID effect causes an increase in the delay and the leakage current of CMOS circuits which may damage the proper operation of the integrated circuit. To ensure proper operation of these devices under radiation, thorough testing must be made especially in critical applications like space and military applications. Although the standard which describes the procedure for testing electronic devices under radiation emphasizes the use of worst case test vectors (WCTVs), they are never used in radiation testing due to the difficulty of generating these vectors for circuits under test. For decades, design for testability (DFT) has been the best choice for test engineers to test digital circuits in industry. It has become a very mature technology that can be relied on. DFT is usually used with automatic test patterns generation (ATPG) software to generate test vectors to test application specific integrated circuits (ASICs), especially with sequential circuits, against faults like stuck at faults and path delay faults. Surprisingly, however, radiation testing has not yet made use of this reliable technology. In this thesis, a novel methodology is proposed to extend the usage of DFT to generate WCTVs for delay failure in Flash based field programmable gate arrays (FPGAs) exposed to total ionizing dose (TID). The methodology is validated using MicroSemi ProASIC3 FPGA and cobalt 60 facility. 2018-06-01T07:00:00Z thesis application/pdf https://fount.aucegypt.edu/etds/1349 https://fount.aucegypt.edu/context/etds/article/2348/viewcontent/Mohamed_20Sami_20M.Sc._20Thesis.pdf The author retains all rights with regard to copyright. The author certifies that written permission from the owner(s) of third-party copyrighted matter included in the thesis, dissertation, paper, or record of study has been obtained. The author further certifies that IRB approval has been obtained for this thesis, or that IRB approval is not necessary for this thesis. Insofar as this thesis, dissertation, paper, or record of study is an educational record as defined in the Family Educational Rights and Privacy Act (FERPA) (20 USC 1232g), the author has granted consent to disclosure of it to anyone who requests a copy. The author has granted the American University in Cairo or its agents a non-exclusive license to archive this thesis, dissertation, paper, or record of study, and to make it accessible, in whole or in part, in all forms of media, now or hereafter known. Theses and Dissertations AUC Knowledge Fountain Design For Testability;Field Programmable Gate Arrays (FPGAs); |
| spellingShingle | Design For Testability;Field Programmable Gate Arrays (FPGAs); Abdelwahab, Mohamed Sami Identifying worst case test vectors for FPGA exposed to total ionization dose using design for testability techniques |
| title | Identifying worst case test vectors for FPGA exposed to total ionization dose using design for testability techniques |
| title_full | Identifying worst case test vectors for FPGA exposed to total ionization dose using design for testability techniques |
| title_fullStr | Identifying worst case test vectors for FPGA exposed to total ionization dose using design for testability techniques |
| title_full_unstemmed | Identifying worst case test vectors for FPGA exposed to total ionization dose using design for testability techniques |
| title_short | Identifying worst case test vectors for FPGA exposed to total ionization dose using design for testability techniques |
| title_sort | identifying worst case test vectors for fpga exposed to total ionization dose using design for testability techniques |
| topic | Design For Testability;Field Programmable Gate Arrays (FPGAs); |
| url | https://fount.aucegypt.edu/etds/1349 https://fount.aucegypt.edu/context/etds/article/2348/viewcontent/Mohamed_20Sami_20M.Sc._20Thesis.pdf |
| work_keys_str_mv | AT abdelwahabmohamedsami identifyingworstcasetestvectorsforfpgaexposedtototalionizationdoseusingdesignfortestabilitytechniques |