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Stochastic Worst-Case Test Vectors for ASIC Devices in Single Event Environment

Charged particles and energetic particles can impact the integrated circuit, referred to as single event effects (SEE). Nuclear reactors and space radiation can produce these particles. These effects can negatively affect the reliability and performance of electronics. When SEE occurs, a transient c...

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Main Author: Hemeda, Mostafa
Format: Thesis
Published: AUC Knowledge Fountain 2023
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_version_ 1867613422902837248
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author Hemeda, Mostafa
author_browse Hemeda, Mostafa
author_facet Hemeda, Mostafa
author_sort Hemeda, Mostafa
collection Thesis
description Charged particles and energetic particles can impact the integrated circuit, referred to as single event effects (SEE). Nuclear reactors and space radiation can produce these particles. These effects can negatively affect the reliability and performance of electronics. When SEE occurs, a transient current is created, which can cause electronic devices to have incorrect outputs and ultimately fail. As a result, ensuring the reliability of ASIC circuits is a significant concern. This thesis discusses the different fault types, then discuss the soft error and, in particular, the Single Event Transient (SET) and its causes and models. Then, this thesis proposes a new model to get the probability of error of standard cells using a pre-characterized cell module. The proposed method guarantees that no logical masking and over-estimation of the probability of error has occurred. Furthermore, it suggests calculating the error probability of the whole combinational circuit in application-specific integrated circuits (ASIC) using the Krishnaswamy method and a newly proposed method. Finally, this thesis presents a new approach to getting the worst-case vector based on Krishnaswamy and a newly proposed method. The flow gets the most probable vector as the worst-case vector from a set of vectors generated from the Automated Test Pattern Generation (ATPG) tool. In addition, a new error metric is discussed to find the worst-case vector based on two-norm.
format Thesis
id oai:fount.aucegypt.edu:etds-3157
institution American University in Cairo (Egypt)
last_indexed 2026-06-10T12:35:54.296Z
license_str Not specified — see source repository
provenance_str_mv Harvested via OAI-PMH from AUC Knowledge Fountain — bepress
publishDate 2023
publishDateRange 2023
publishDateSort 2023
publisher AUC Knowledge Fountain
publisherStr AUC Knowledge Fountain
record_format dspace
source_str AUC Knowledge Fountain — bepress
spelling oai:fount.aucegypt.edu:etds-3157 Stochastic Worst-Case Test Vectors for ASIC Devices in Single Event Environment Hemeda, Mostafa Charged particles and energetic particles can impact the integrated circuit, referred to as single event effects (SEE). Nuclear reactors and space radiation can produce these particles. These effects can negatively affect the reliability and performance of electronics. When SEE occurs, a transient current is created, which can cause electronic devices to have incorrect outputs and ultimately fail. As a result, ensuring the reliability of ASIC circuits is a significant concern. This thesis discusses the different fault types, then discuss the soft error and, in particular, the Single Event Transient (SET) and its causes and models. Then, this thesis proposes a new model to get the probability of error of standard cells using a pre-characterized cell module. The proposed method guarantees that no logical masking and over-estimation of the probability of error has occurred. Furthermore, it suggests calculating the error probability of the whole combinational circuit in application-specific integrated circuits (ASIC) using the Krishnaswamy method and a newly proposed method. Finally, this thesis presents a new approach to getting the worst-case vector based on Krishnaswamy and a newly proposed method. The flow gets the most probable vector as the worst-case vector from a set of vectors generated from the Automated Test Pattern Generation (ATPG) tool. In addition, a new error metric is discussed to find the worst-case vector based on two-norm. 2023-06-21T07:00:00Z thesis application/pdf https://fount.aucegypt.edu/etds/2120 https://fount.aucegypt.edu/context/etds/article/3157/viewcontent/Mostafa_Abdelmohsen_Hemeda_thesis.pdf Theses and Dissertations AUC Knowledge Fountain soft errors single-event effects worst-case vector single-event upsets SEE SET radiative particles probability of error. Electrical and Electronics
spellingShingle soft errors
single-event effects
worst-case vector
single-event upsets
SEE
SET
radiative particles
probability of error.
Electrical and Electronics
Hemeda, Mostafa
Stochastic Worst-Case Test Vectors for ASIC Devices in Single Event Environment
title Stochastic Worst-Case Test Vectors for ASIC Devices in Single Event Environment
title_full Stochastic Worst-Case Test Vectors for ASIC Devices in Single Event Environment
title_fullStr Stochastic Worst-Case Test Vectors for ASIC Devices in Single Event Environment
title_full_unstemmed Stochastic Worst-Case Test Vectors for ASIC Devices in Single Event Environment
title_short Stochastic Worst-Case Test Vectors for ASIC Devices in Single Event Environment
title_sort stochastic worst case test vectors for asic devices in single event environment
topic soft errors
single-event effects
worst-case vector
single-event upsets
SEE
SET
radiative particles
probability of error.
Electrical and Electronics
url https://fount.aucegypt.edu/etds/2120
https://fount.aucegypt.edu/context/etds/article/3157/viewcontent/Mostafa_Abdelmohsen_Hemeda_thesis.pdf
work_keys_str_mv AT hemedamostafa stochasticworstcasetestvectorsforasicdevicesinsingleeventenvironment