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Flexible Fault-Tolerant Multi-Die FPGA-based Architectures for Varying Space Environments
It is well-known fact that spacecraft’s electronic components operate in an extreme harsh and varying space environments, beside changing orbit or passing through Van Allan Belts during orbital course results of radiation levels change. This thesis focuses on SRAM-based FPGA systems on-board of such...
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| Format: | Thesis |
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AUC Knowledge Fountain
2026
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| Summary: | It is well-known fact that spacecraft’s electronic components operate in an extreme harsh and varying space environments, beside changing orbit or passing through Van Allan Belts during orbital course results of radiation levels change. This thesis focuses on SRAM-based FPGA systems on-board of such spacecrafts, that are commonly utilized in space applications’ critical applications due to their capabilities and flexibility to reconfigure, since these systems are vulnerable to frequent negative impacts of ionizing radiation, thus inducing soft and hard errors leading to disastrous failures that could jeopardize the entire spacecraft. The soft errors’ effects are frequent yet can be mitigated, specifically SEUs and DEUs, through fault tolerance techniques, which are an essential feature in critical systems. However, this approach relies on redundant components that use finite FPGA resources, so replication is limited. This Thesis proposes multi-die FPGA of different technology nodes to capitalize on reliably older technology while benefits from speed and performance of newer technology dice. Varity of fault tolerance architectures’ designs will be investigated in various scenarios of limited area, as well as resilience to high rate of certain types of event upsets exposure, to identify what changes are required in the common and known technique for achieving comparably elevated reliability. CTMCs utilization for calculating architecture reliability in different placement strategies is essential for maximizing system’s operation lifetime. Several case studies illustrate utilization of these techniques on a Xilinx FPGA, and resulted case-by-case reliability are listed after simulation by SHARPE package tool to support recommendation and conclusion. |
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