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A Novel Design-for-Test flow using LibreLane
Design-for-testing is a crucial element of application-specific integrated circuit design, yet, in the nascent open-source electronic design automation scene, the solutions for it are sorely limited. Design-for-test-enabled chips allow defects to be caught early on in the manufacturing process, avoi...
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| Format: | Thesis |
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AUC Knowledge Fountain
2026
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| _version_ | 1867613434083803136 |
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| access_status_str | Open Access |
| author | Gaber, Mohamed E |
| author_browse | Gaber, Mohamed E |
| author_facet | Gaber, Mohamed E |
| author_sort | Gaber, Mohamed E |
| collection | Thesis |
| description | Design-for-testing is a crucial element of application-specific integrated circuit design, yet, in the nascent open-source electronic design automation scene, the solutions for it are sorely limited. Design-for-test-enabled chips allow defects to be caught early on in the manufacturing process, avoiding incurring huge costs if hardware with defective chips is shipped to equipment manufacturers or, worse, end-users. Yet, the current open-source solutions rely on a brute-force utility that does not scale and negatively impacts the design by holding design-for-testing features as co-equal with the design’s regular operation, and a nominally layout-aware solution that does not holistically integrate into a larger flow.
This work architects and implements a novel design-for-test flow designed as a plugin for the popular LibreLane flow infrastructure, the successor to the single most used application-specific integrated circuit design flow in existence. Coalescing a number of existing and ad-hoc developed open-source tools, it shows that open-source electronic design automation tools can indeed be used to create macros and chips that are design-for-testing-enabled, with rapid test pattern generation, area savings by using scannable flip-flops, as well as layout-aware placement that appreciably decreases routing time in comparison to existing approaches.
It investigates various strategies for ordering of a scan chain, comparing the current approaches of ordering a netlist, or a greedy closest-first algorithm, to the decades of work on optimizing the traveling salesman problem. It compares the results across three strategies and two process design kits. |
| format | Thesis |
| id | oai:fount.aucegypt.edu:etds-3842 |
| institution | American University in Cairo (Egypt) |
| last_indexed | 2026-06-10T12:36:04.810Z |
| license_str | Not specified — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from AUC Knowledge Fountain — bepress |
| publishDate | 2026 |
| publishDateRange | 2026 |
| publishDateSort | 2026 |
| publisher | AUC Knowledge Fountain |
| publisherStr | AUC Knowledge Fountain |
| record_format | dspace |
| source_str | AUC Knowledge Fountain — bepress |
| spelling | oai:fount.aucegypt.edu:etds-3842 A Novel Design-for-Test flow using LibreLane Gaber, Mohamed E Design-for-testing is a crucial element of application-specific integrated circuit design, yet, in the nascent open-source electronic design automation scene, the solutions for it are sorely limited. Design-for-test-enabled chips allow defects to be caught early on in the manufacturing process, avoiding incurring huge costs if hardware with defective chips is shipped to equipment manufacturers or, worse, end-users. Yet, the current open-source solutions rely on a brute-force utility that does not scale and negatively impacts the design by holding design-for-testing features as co-equal with the design’s regular operation, and a nominally layout-aware solution that does not holistically integrate into a larger flow. This work architects and implements a novel design-for-test flow designed as a plugin for the popular LibreLane flow infrastructure, the successor to the single most used application-specific integrated circuit design flow in existence. Coalescing a number of existing and ad-hoc developed open-source tools, it shows that open-source electronic design automation tools can indeed be used to create macros and chips that are design-for-testing-enabled, with rapid test pattern generation, area savings by using scannable flip-flops, as well as layout-aware placement that appreciably decreases routing time in comparison to existing approaches. It investigates various strategies for ordering of a scan chain, comparing the current approaches of ordering a netlist, or a greedy closest-first algorithm, to the decades of work on optimizing the traveling salesman problem. It compares the results across three strategies and two process design kits. 2026-06-11T07:00:00Z thesis application/pdf https://fount.aucegypt.edu/etds/2779 https://fount.aucegypt.edu/context/etds/article/3842/viewcontent/thesis_final.pdf Theses and Dissertations AUC Knowledge Fountain chip design silicon design open-source design flows silicon flows ASIC DFT Digital Circuits |
| spellingShingle | chip design silicon design open-source design flows silicon flows ASIC DFT Digital Circuits Gaber, Mohamed E A Novel Design-for-Test flow using LibreLane |
| title | A Novel Design-for-Test flow using LibreLane |
| title_full | A Novel Design-for-Test flow using LibreLane |
| title_fullStr | A Novel Design-for-Test flow using LibreLane |
| title_full_unstemmed | A Novel Design-for-Test flow using LibreLane |
| title_short | A Novel Design-for-Test flow using LibreLane |
| title_sort | novel design for test flow using librelane |
| topic | chip design silicon design open-source design flows silicon flows ASIC DFT Digital Circuits |
| url | https://fount.aucegypt.edu/etds/2779 https://fount.aucegypt.edu/context/etds/article/3842/viewcontent/thesis_final.pdf |
| work_keys_str_mv | AT gabermohamede anoveldesignfortestflowusinglibrelane AT gabermohamede noveldesignfortestflowusinglibrelane |