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Physical Effects on the Worst-Case Delay Analysis and Signal Integrity of Buses and Spirals
Physical effects have a significant impact on the IC design which will be investigated in this thesis. Moving toward advanced technology nodes, magnetic effects become more dominant than capacitive effects. As the dimensions of the devices go down and the interconnect manipulates the circuit behavio...
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AUC Knowledge Fountain
2024
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| _version_ | 1867613424034250752 |
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| access_status_str | Open Access |
| author | Mahany, Mahmoud |
| author_browse | Mahany, Mahmoud |
| author_facet | Mahany, Mahmoud |
| author_sort | Mahany, Mahmoud |
| collection | Thesis |
| description | Physical effects have a significant impact on the IC design which will be investigated in this thesis. Moving toward advanced technology nodes, magnetic effects become more dominant than capacitive effects. As the dimensions of the devices go down and the interconnect manipulates the circuit behavior more and more. Cross talking and voltage drops are affecting the design heavily, however - going to the full electromagnetic point of view - current return path (CRP) adds significant parasitics to the performance of the chip. Neglecting the CRP gives wrong intuition and simulation of the designs, especially that the environment and surroundings can play an important role in defining the current return path. Signal delay and worst-case delay switch pattern can vary significantly when including magnetics and current return path. Image current for spirals significantly affects the inductance value. In the following chapters those phenomena will be discussed together with the ways to minimize their effects. |
| format | Thesis |
| id | oai:fount.aucegypt.edu:etds-3380 |
| institution | American University in Cairo (Egypt) |
| last_indexed | 2026-06-10T12:35:55.364Z |
| license_str | Not specified — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from AUC Knowledge Fountain — bepress |
| publishDate | 2024 |
| publishDateRange | 2024 |
| publishDateSort | 2024 |
| publisher | AUC Knowledge Fountain |
| publisherStr | AUC Knowledge Fountain |
| record_format | dspace |
| source_str | AUC Knowledge Fountain — bepress |
| spelling | oai:fount.aucegypt.edu:etds-3380 Physical Effects on the Worst-Case Delay Analysis and Signal Integrity of Buses and Spirals Mahany, Mahmoud Physical effects have a significant impact on the IC design which will be investigated in this thesis. Moving toward advanced technology nodes, magnetic effects become more dominant than capacitive effects. As the dimensions of the devices go down and the interconnect manipulates the circuit behavior more and more. Cross talking and voltage drops are affecting the design heavily, however - going to the full electromagnetic point of view - current return path (CRP) adds significant parasitics to the performance of the chip. Neglecting the CRP gives wrong intuition and simulation of the designs, especially that the environment and surroundings can play an important role in defining the current return path. Signal delay and worst-case delay switch pattern can vary significantly when including magnetics and current return path. Image current for spirals significantly affects the inductance value. In the following chapters those phenomena will be discussed together with the ways to minimize their effects. 2024-06-12T07:00:00Z thesis application/pdf https://fount.aucegypt.edu/etds/2336 https://fount.aucegypt.edu/context/etds/article/3380/viewcontent/Mahmoud_MohammedSalahAldeenYassin_Mahany_thesis.pdf Theses and Dissertations AUC Knowledge Fountain Current Return Path IC PCB Substrate Electromagnetic Fields CAD Electrical and Electronics Electronic Devices and Semiconductor Manufacturing VLSI and Circuits, Embedded and Hardware Systems |
| spellingShingle | Current Return Path IC PCB Substrate Electromagnetic Fields CAD Electrical and Electronics Electronic Devices and Semiconductor Manufacturing VLSI and Circuits, Embedded and Hardware Systems Mahany, Mahmoud Physical Effects on the Worst-Case Delay Analysis and Signal Integrity of Buses and Spirals |
| title | Physical Effects on the Worst-Case Delay Analysis and Signal Integrity of Buses and Spirals |
| title_full | Physical Effects on the Worst-Case Delay Analysis and Signal Integrity of Buses and Spirals |
| title_fullStr | Physical Effects on the Worst-Case Delay Analysis and Signal Integrity of Buses and Spirals |
| title_full_unstemmed | Physical Effects on the Worst-Case Delay Analysis and Signal Integrity of Buses and Spirals |
| title_short | Physical Effects on the Worst-Case Delay Analysis and Signal Integrity of Buses and Spirals |
| title_sort | physical effects on the worst case delay analysis and signal integrity of buses and spirals |
| topic | Current Return Path IC PCB Substrate Electromagnetic Fields CAD Electrical and Electronics Electronic Devices and Semiconductor Manufacturing VLSI and Circuits, Embedded and Hardware Systems |
| url | https://fount.aucegypt.edu/etds/2336 https://fount.aucegypt.edu/context/etds/article/3380/viewcontent/Mahmoud_MohammedSalahAldeenYassin_Mahany_thesis.pdf |
| work_keys_str_mv | AT mahanymahmoud physicaleffectsontheworstcasedelayanalysisandsignalintegrityofbusesandspirals |