Full Text Available
Note: Clicking the button above will open the full text document at the original institutional repository in a new window.
Gate-level superconductor integrated circuit fabrication process modelling for improved layout extraction
Thesis (MEng)--Stellenbosch University, 2021.
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Language: | en_ZA |
| Published: |
Stellenbosch : Stellenbosch University, 2021.
2021
|
| Subjects: | |
| Tags: |
No Tags, Be the first to tag this record!
|
| _version_ | 1867613971443351552 |
|---|---|
| access_status_str | Open Access |
| author | Herbst, Heinrich |
| author2 | Fourie, Coenrad |
| author_browse | Fourie, Coenrad Herbst, Heinrich |
| author_facet | Fourie, Coenrad Herbst, Heinrich |
| author_sort | Herbst, Heinrich |
| collection | Thesis |
| dc_rights_str_mv | Stellenbosch University |
| description | Thesis (MEng)--Stellenbosch University, 2021. |
| format | Thesis |
| id | oai:scholar.sun.ac.za:10019.1/109818 |
| institution | Stellenbosch University (South Africa) |
| language | en_ZA |
| last_indexed | 2026-06-10T12:44:37.487Z |
| license_str | Other — see source repository |
| provenance_str_mv | Harvested via OAI-PMH from SUNScholar — Stellenbosch University Repository |
| publishDate | 2021 |
| publishDateRange | 2021 |
| publishDateSort | 2021 |
| publisher | Stellenbosch : Stellenbosch University, 2021. |
| publisherStr | Stellenbosch : Stellenbosch University, 2021. |
| record_format | dspace |
| source_str | SUNScholar — Stellenbosch University Repository |
| spelling | oai:scholar.sun.ac.za:10019.1/109818 Gate-level superconductor integrated circuit fabrication process modelling for improved layout extraction Herbst, Heinrich Fourie, Coenrad Stellenbosch University. Faculty of Engineering. Faculty of Engineering. Dept. of Electrical and Electronic Engineering. Integrated circuit layout UCTD Superconductors Integrated Circuit Process Modelling Thesis (MEng)--Stellenbosch University, 2021. ENGLISH ABSTRACT: This thesis presents the development of a fabrication process modelling tool called Katana, created to aid in parameter extraction of superconducting electronic (SCE) integrated circuit (IC) layouts. The program forms part of a toolchain for the development of superconducting technology-based computers. The thesis begins with an overview of the fabrication process of SCE ICs, following which the implementation of Katana is discussed in two chapters. The first chapter on implementation describes a module which generates twodimensional circuit cross-sections when provided with the mask layout and fabrication process data. The module also assists with manual 3D modelling of circuit elements using strategic slices from the University of Florida’s process modelling tool, FLOOXS. The next chapter describes the implementation of an automated, three-dimensional SCE logic-gate modelling module. The module is capable of automatically generating process-modelled circuit representations which can be meshed and fed into finite-element parameter extraction software. The thesis reviews the functionality of the program by generating and analyzing models of Rapid Single Flux Quantum- (RSFQ-)- based superconducting circuit logic gates and confirms the necessity of process modelling through a discussion on how the enhanced models affect parameter extraction. Additionally, the thesis shows that researchers are already using Katana for improved thermal analysis and current density simulation. The concluding section discusses potential further research in future. AFRIKAANSE OPSOMMING: Hierdie tesis beskryf die ontwikkeling van ’n vervaardigingsproses-modelleerinstrument genaamd Katana, wat geskep is om met die parameterekstraksie van supergeleierelektroniese (Eng. SCE) geïntegreerde stroombaanuitlegte (Eng. IC-uitlegte) te help. Die program vorm deel van ’n gereedskapsketting vir die ontwikkeling van supergeleidende-tegnologie-gebaseerde rekenaars. Die tesis bied eers ’n oorsig van die vervaardigingsproses van die stroombane, waarna die implementering van Katana in twee hoofstukke bespreek word. Die eerste implementeringshoofstuk beskryf ’n module wat tweedimensionele stroomdeursnitte genereer wanneer die maskeruitleg en vervaardigingsprosesdata ingevoer word. Die module help ook met die 3D-modellering van stroombaanelemente met die hand, met behulp van strategiese snitte vanuit die Universiteit van Florida se prosesmodelleerder, FLOOXS. Die daaropvolgende hoofstuk beskryf die implementering van ’n geoutomatiseerde, driedimensionele SCE logiesehekmodellering-module. Die module is in staat om prosesgemodelleerde stroombaanvoorstellings outomaties te genereer, wat saamgevoeg en by eindige-element-parameterekstraksiesagteware ingevoer kan word. Die funksionaliteit van die program word ondersoek deur modelle van “rapid single flux quantum”-gebaseerde (RSFQ) supergeleidende-stroombaan- logiese hekke te genereer en te ontleed. ’n Bespreking van die uitwerking van verbeterde modelle op parameterekstraksie bevestig die noodsaaklikheid van prosesmodellering. Daarbenewens word aangetoon dat navorsers Katana reeds vir verbeterde termiese ontleding en stroomdigtheidsimulasie gebruik. Die tesis sluit af met ’n bespreking van die potensiaal vir toekomstige verdere navorsing. Masters 2021-02-04T05:17:14Z 2021-04-21T14:27:29Z 2021-02-04T05:17:14Z 2021-04-21T14:27:29Z 2021-03 Thesis http://hdl.handle.net/10019.1/109818 en_ZA Stellenbosch University 124 pages application/pdf Stellenbosch : Stellenbosch University, 2021. |
| spellingShingle | Integrated circuit layout UCTD Superconductors Integrated Circuit Process Modelling Herbst, Heinrich Gate-level superconductor integrated circuit fabrication process modelling for improved layout extraction |
| title | Gate-level superconductor integrated circuit fabrication process modelling for improved layout extraction |
| title_full | Gate-level superconductor integrated circuit fabrication process modelling for improved layout extraction |
| title_fullStr | Gate-level superconductor integrated circuit fabrication process modelling for improved layout extraction |
| title_full_unstemmed | Gate-level superconductor integrated circuit fabrication process modelling for improved layout extraction |
| title_short | Gate-level superconductor integrated circuit fabrication process modelling for improved layout extraction |
| title_sort | gate level superconductor integrated circuit fabrication process modelling for improved layout extraction |
| topic | Integrated circuit layout UCTD Superconductors Integrated Circuit Process Modelling |
| url | http://hdl.handle.net/10019.1/109818 |
| work_keys_str_mv | AT herbstheinrich gatelevelsuperconductorintegratedcircuitfabricationprocessmodellingforimprovedlayoutextraction |