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Single Event Transient Sensitivity Measurement and Worst-Case Test Vector Exploration for ASIC Devices Exposed to Space Single Event Environment

Space radiation and nuclear reactors produce single event effects (SEE) in electronic circuits and impact their performance. The SEE phenomena cause circuits and electronic devices to fail by producing faulty results. Therefore, today’s circuit’s reliability is a significant concern for all circuit...

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Main Author: Wael, Mohamed
Format: Thesis
Published: AUC Knowledge Fountain 2022
Subjects:
single event effects; single event upset; SET fault; ASIC; CMOS; SET sensitivity; reliability; worst-case test vector; space environment;
Electrical and Electronics
VLSI and Circuits, Embedded and Hardware Systems
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access_status_str Open Access
author Wael, Mohamed
author_browse Wael, Mohamed
author_facet Wael, Mohamed
author_sort Wael, Mohamed
collection Thesis
description Space radiation and nuclear reactors produce single event effects (SEE) in electronic circuits and impact their performance. The SEE phenomena cause circuits and electronic devices to fail by producing faulty results. Therefore, today’s circuit’s reliability is a significant concern for all circuit designers. This thesis suggests a new automated flow to measure the single-event-transient (SET) effects in combinational circuits in application-specific integrated circuits (ASIC) while reaching full fault coverage. The developed flow characterizes the whole circuit nodes by identifying the most sensitive paths to the propagated SET pulses from the node under test to an observable primary output, causing single event upsets (SEUs). The flow generates test vectors to reach the combinational circuit's highest possible fault coverage percentage. The generated test vectors guarantee that no logical masking for detected SET faults. Then, it analyzes each test vector independently to detect different sensitized paths possible for SET fault propagation. Then, the flow searches for the most sensitive path from the node under test to an observable primary output while measuring the minimal SET pulse characteristics that would produce SEUs. This approach also suggests a new enhanced metric is to identify which test vector enhances the propagated SET pulse within a combinational circuit, which is vital to find worst-case test vectors.
format Thesis
id oai:fount.aucegypt.edu:etds-2913
institution American University in Cairo (Egypt)
last_indexed 2026-06-10T12:35:53.165Z
license_str Not specified — see source repository
provenance_str_mv Harvested via OAI-PMH from AUC Knowledge Fountain — bepress
publishDate 2022
publishDateRange 2022
publishDateSort 2022
publisher AUC Knowledge Fountain
publisherStr AUC Knowledge Fountain
record_format dspace
source_str AUC Knowledge Fountain — bepress
spelling oai:fount.aucegypt.edu:etds-2913 Single Event Transient Sensitivity Measurement and Worst-Case Test Vector Exploration for ASIC Devices Exposed to Space Single Event Environment Wael, Mohamed Space radiation and nuclear reactors produce single event effects (SEE) in electronic circuits and impact their performance. The SEE phenomena cause circuits and electronic devices to fail by producing faulty results. Therefore, today’s circuit’s reliability is a significant concern for all circuit designers. This thesis suggests a new automated flow to measure the single-event-transient (SET) effects in combinational circuits in application-specific integrated circuits (ASIC) while reaching full fault coverage. The developed flow characterizes the whole circuit nodes by identifying the most sensitive paths to the propagated SET pulses from the node under test to an observable primary output, causing single event upsets (SEUs). The flow generates test vectors to reach the combinational circuit's highest possible fault coverage percentage. The generated test vectors guarantee that no logical masking for detected SET faults. Then, it analyzes each test vector independently to detect different sensitized paths possible for SET fault propagation. Then, the flow searches for the most sensitive path from the node under test to an observable primary output while measuring the minimal SET pulse characteristics that would produce SEUs. This approach also suggests a new enhanced metric is to identify which test vector enhances the propagated SET pulse within a combinational circuit, which is vital to find worst-case test vectors. 2022-01-13T08:00:00Z thesis application/pdf https://fount.aucegypt.edu/etds/1934 https://fount.aucegypt.edu/context/etds/article/2913/viewcontent/mohamed_wael_mohamed_nady_thesis.pdf Theses and Dissertations AUC Knowledge Fountain single event effects; single event upset; SET fault; ASIC; CMOS; SET sensitivity; reliability; worst-case test vector; space environment; Electrical and Electronics VLSI and Circuits, Embedded and Hardware Systems
spellingShingle single event effects; single event upset; SET fault; ASIC; CMOS; SET sensitivity; reliability; worst-case test vector; space environment;
Electrical and Electronics
VLSI and Circuits, Embedded and Hardware Systems
Wael, Mohamed
Single Event Transient Sensitivity Measurement and Worst-Case Test Vector Exploration for ASIC Devices Exposed to Space Single Event Environment
title Single Event Transient Sensitivity Measurement and Worst-Case Test Vector Exploration for ASIC Devices Exposed to Space Single Event Environment
title_full Single Event Transient Sensitivity Measurement and Worst-Case Test Vector Exploration for ASIC Devices Exposed to Space Single Event Environment
title_fullStr Single Event Transient Sensitivity Measurement and Worst-Case Test Vector Exploration for ASIC Devices Exposed to Space Single Event Environment
title_full_unstemmed Single Event Transient Sensitivity Measurement and Worst-Case Test Vector Exploration for ASIC Devices Exposed to Space Single Event Environment
title_short Single Event Transient Sensitivity Measurement and Worst-Case Test Vector Exploration for ASIC Devices Exposed to Space Single Event Environment
title_sort single event transient sensitivity measurement and worst case test vector exploration for asic devices exposed to space single event environment
topic single event effects; single event upset; SET fault; ASIC; CMOS; SET sensitivity; reliability; worst-case test vector; space environment;
Electrical and Electronics
VLSI and Circuits, Embedded and Hardware Systems
url https://fount.aucegypt.edu/etds/1934
https://fount.aucegypt.edu/context/etds/article/2913/viewcontent/mohamed_wael_mohamed_nady_thesis.pdf
work_keys_str_mv AT waelmohamed singleeventtransientsensitivitymeasurementandworstcasetestvectorexplorationforasicdevicesexposedtospacesingleeventenvironment

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